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# Xilinx CORE Generator 3.1i_ip_update3
# Username = avisha
# COREGenPath = D:\Xilinx\coregen
# ProjectPath = \\Lodn001\Tmp\projects\bender\coregen
# ExpandedProjectPath = \\Lodn001\Tmp\projects\bender\coregen
SET BusFormat = BusFormatParen
SET SimulationOutputProducts = Verilog
SET ViewlogicLibraryAlias = ""
SET XilinxFamily = Virtex
SET DesignFlow = Verilog
SET FlowVendor = Exemplar
SELECT Asynchronous_FIFO Virtex Xilinx,_Inc. 3.0
CSET write_error = false
CSET component_name = fifo_4095_16
CSET write_error_sense = active_high
CSET read_count_width = 2
CSET read_error = false
CSET read_error_sense = active_high
CSET write_count = false
CSET write_acknowledge = false
CSET memory_type = block
CSET read_acknowledge_sense = active_high
CSET fifo_depth = 4095
CSET read_count = false
CSET almost_full_flag = true
CSET read_acknowledge = false
CSET almost_empty_flag = true
CSET input_data_width = 16
CSET write_count_width = 2
CSET create_rpm = false
CSET write_acknowledge_sense = active_high
GENERATE