URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [FDCP_1.v] - Rev 266
Go to most recent revision | Compare with Previous | Blame | View Log
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/FDCP_1.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $ /* FUNCTION : D-FLIP-FLOP with async clear, async preset */ `timescale 100 ps / 10 ps `celldefine module FDCP_1 (Q, C, CLR, D, PRE); parameter cds_action = "ignore"; parameter INIT = 1'b0; output Q; reg q_out; input C, CLR, D, PRE; tri0 GSR = glbl.GSR; buf B1 (Q, q_out); always @(GSR or CLR or PRE) if (GSR) assign q_out = INIT; else if (CLR) assign q_out = 0; else if (PRE) assign q_out = 1; else deassign q_out; always @(negedge C) q_out <= D; specify (posedge CLR => (Q +: 1'b0)) = (1, 1); if (!CLR) (posedge PRE => (Q +: 1'b1)) = (1, 1); if (!CLR && !PRE) (negedge C => (Q +: D)) = (1, 1); endspecify endmodule `endcelldefine
Go to most recent revision | Compare with Previous | Blame | View Log