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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [cfgr.v] - Rev 317
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's VR, UPR and Configuration Registers //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// According to OR1K architectural and OR1200 specifications. //// //// //// //// To Do: //// //// - done //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:35 igorm // no message // // Revision 1.1 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:21 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" module cfgr( // RISC Internal Interface clk, rst, spr_addr, spr_dat_o ); // // RISC Internal Interface // input clk; // Clock input rst; // Reset input [31:0] spr_addr; // SPR Address output [31:0] spr_dat_o; // SPR Read Data // // Internal wires & registers // reg [31:0] spr_dat_o; // SPR Read Data `ifdef CFGR_IMPLEMENTED // // Implementation of VR, UPR and configuration registers // always @(spr_addr) `ifdef SYS_FULL_DECODE if (!spr_addr[31:4]) `endif case(spr_addr[3:0]) `SPRGRP_SYS_VR: begin spr_dat_o[`VR_REV_BITS] = `VR_REV; spr_dat_o[`VR_RES1_BITS] = `VR_RES1; spr_dat_o[`VR_CFG_BITS] = `VR_CFG; spr_dat_o[`VR_VER_BITS] = `VR_VER; end `SPRGRP_SYS_UPR: begin spr_dat_o[`UPR_UP_BITS] = `UPR_UP; spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP; spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP; spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP; spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP; spr_dat_o[`UPR_MP_BITS] = `UPR_MP; spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP; spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP; spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP; spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP; spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP; spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1; spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP; end `SPRGRP_SYS_CPUCFGR: begin spr_dat_o[`CPUCFGR_NSGF_BITS] = `CPUCFGR_NSGF; spr_dat_o[`CPUCFGR_HGF_BITS] = `CPUCFGR_HGF; spr_dat_o[`CPUCFGR_OB32S_BITS] = `CPUCFGR_OB32S; spr_dat_o[`CPUCFGR_OB64S_BITS] = `CPUCFGR_OB64S; spr_dat_o[`CPUCFGR_OF32S_BITS] = `CPUCFGR_OF32S; spr_dat_o[`CPUCFGR_OF64S_BITS] = `CPUCFGR_OF64S; spr_dat_o[`CPUCFGR_OV64S_BITS] = `CPUCFGR_OV64S; spr_dat_o[`CPUCFGR_RES1_BITS] = `CPUCFGR_RES1; end `SPRGRP_SYS_DMMUCFGR: begin spr_dat_o[`DMMUCFGR_NTW_BITS] = `DMMUCFGR_NTW; spr_dat_o[`DMMUCFGR_NTS_BITS] = `DMMUCFGR_NTS; spr_dat_o[`DMMUCFGR_NAE_BITS] = `DMMUCFGR_NAE; spr_dat_o[`DMMUCFGR_CRI_BITS] = `DMMUCFGR_CRI; spr_dat_o[`DMMUCFGR_PRI_BITS] = `DMMUCFGR_PRI; spr_dat_o[`DMMUCFGR_TEIRI_BITS] = `DMMUCFGR_TEIRI; spr_dat_o[`DMMUCFGR_HTR_BITS] = `DMMUCFGR_HTR; spr_dat_o[`DMMUCFGR_RES1_BITS] = `DMMUCFGR_RES1; end `SPRGRP_SYS_IMMUCFGR: begin spr_dat_o[`IMMUCFGR_NTW_BITS] = `IMMUCFGR_NTW; spr_dat_o[`IMMUCFGR_NTS_BITS] = `IMMUCFGR_NTS; spr_dat_o[`IMMUCFGR_NAE_BITS] = `IMMUCFGR_NAE; spr_dat_o[`IMMUCFGR_CRI_BITS] = `IMMUCFGR_CRI; spr_dat_o[`IMMUCFGR_PRI_BITS] = `IMMUCFGR_PRI; spr_dat_o[`IMMUCFGR_TEIRI_BITS] = `IMMUCFGR_TEIRI; spr_dat_o[`IMMUCFGR_HTR_BITS] = `IMMUCFGR_HTR; spr_dat_o[`IMMUCFGR_RES1_BITS] = `IMMUCFGR_RES1; end `SPRGRP_SYS_DCCFGR: begin spr_dat_o[`DCCFGR_NCW_BITS] = `DCCFGR_NCW; spr_dat_o[`DCCFGR_NCS_BITS] = `DCCFGR_NCS; spr_dat_o[`DCCFGR_CBS_BITS] = `DCCFGR_CBS; spr_dat_o[`DCCFGR_CWS_BITS] = `DCCFGR_CWS; spr_dat_o[`DCCFGR_CCRI_BITS] = `DCCFGR_CCRI; spr_dat_o[`DCCFGR_CBIRI_BITS] = `DCCFGR_CBIRI; spr_dat_o[`DCCFGR_CBPRI_BITS] = `DCCFGR_CBPRI; spr_dat_o[`DCCFGR_CBLRI_BITS] = `DCCFGR_CBLRI; spr_dat_o[`DCCFGR_CBFRI_BITS] = `DCCFGR_CBFRI; spr_dat_o[`DCCFGR_CBWBRI_BITS] = `DCCFGR_CBWBRI; spr_dat_o[`DCCFGR_RES1_BITS] = `DCCFGR_RES1; end `SPRGRP_SYS_ICCFGR: begin spr_dat_o[`ICCFGR_NCW_BITS] = `ICCFGR_NCW; spr_dat_o[`ICCFGR_NCS_BITS] = `ICCFGR_NCS; spr_dat_o[`ICCFGR_CBS_BITS] = `ICCFGR_CBS; spr_dat_o[`ICCFGR_CWS_BITS] = `ICCFGR_CWS; spr_dat_o[`ICCFGR_CCRI_BITS] = `ICCFGR_CCRI; spr_dat_o[`ICCFGR_CBIRI_BITS] = `ICCFGR_CBIRI; spr_dat_o[`ICCFGR_CBPRI_BITS] = `ICCFGR_CBPRI; spr_dat_o[`ICCFGR_CBLRI_BITS] = `ICCFGR_CBLRI; spr_dat_o[`ICCFGR_CBFRI_BITS] = `ICCFGR_CBFRI; spr_dat_o[`ICCFGR_CBWBRI_BITS] = `ICCFGR_CBWBRI; spr_dat_o[`ICCFGR_RES1_BITS] = `ICCFGR_RES1; end `SPRGRP_SYS_DCFGR: begin spr_dat_o[`DCFGR_NDP_BITS] = `DCFGR_NDP; spr_dat_o[`DCFGR_WPCI_BITS] = `DCFGR_WPCI; spr_dat_o[`DCFGR_RES1_BITS] = `DCFGR_RES1; end default: spr_dat_o = 32'h0000_0000; endcase `ifdef SYS_FULL_DECODE else spr_dat_o = 32'h0000_0000; `endif `else // // When configuration registers are not implemented, only // implement VR and UPR // always @(spr_addr) `ifdef SYS_FULL_DECODE if (!spr_addr[31:4]) `endif case(spr_addr[3:0]) `SPRGRP_SYS_VR: begin spr_dat_o[`VR_REV_BITS] = `VR_REV; spr_dat_o[`VR_RES1_BITS] = `VR_RES1; spr_dat_o[`VR_CFG_BITS] = `VR_CFG; spr_dat_o[`VR_VER_BITS] = `VR_VER; end `SPRGRP_SYS_UPR: begin spr_dat_o[`UPR_UP_BITS] = `UPR_UP; spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP; spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP; spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP; spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP; spr_dat_o[`UPR_MP_BITS] = `UPR_MP; spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP; spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP; spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP; spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP; spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP; spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1; spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP; end default: spr_dat_o = 32'h0000_0000; endcase `ifdef SYS_FULL_DECODE else spr_dat_o = 32'h0000_0000; `endif `endif endmodule
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