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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input	[1:0]			addr;
input	[`LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		memdata;
output	[width-1:0]		regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef MEM2REG_FAST
 
`define SEL_00 2'b00
`define SEL_01 2'b01
`define SEL_10 2'b10
`define SEL_11 2'b11
 
reg	[width-1:0]		regdata;
reg	[width-1:0]		aligned;
reg	[1:0]			sel_byte0, sel_byte1,
				sel_byte2, sel_byte3;
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b01x, 2'b00}:
			sel_byte0 = `SEL_11;
		{3'b01x, 2'b01}:
			sel_byte0 = `SEL_10;
		{3'b01x, 2'b10}:
			sel_byte0 = `SEL_01;
		{3'b01x, 2'b11}:
			sel_byte0 = `SEL_00;
		{3'b10x, 2'b00}:
			sel_byte0 = `SEL_10;
		{3'b10x, 2'b10}:
			sel_byte0 = `SEL_00;
		default:
			sel_byte0 = `SEL_00;
	endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx}:
			sel_byte1 = `SEL_00;	// zero extend
		{3'b011, 2'bxx}:
			sel_byte1 = `SEL_10;	// sign extend byte
		{3'b10x, 2'b00}:
			sel_byte1 = `SEL_11;
		default:
			sel_byte1 = `SEL_01;
	endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte2 = `SEL_00;	// zero extend
		{3'b011, 2'bxx}:
			sel_byte2 = `SEL_01;	// sign extend byte
		{3'b101, 2'bxx}:
			sel_byte2 = `SEL_11;	// sign extend halfword
		default:
			sel_byte2 = `SEL_10;
	endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte3 = `SEL_00;	// zero extend
		{3'b011, 2'bxx}:
			sel_byte3 = `SEL_01;	// sign extend byte
		{3'b101, 2'bxx}:
			sel_byte3 = `SEL_10;	// sign extend halfword
		default:
			sel_byte3 = `SEL_11;
	endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
	case(sel_byte0) // synopsys full_case parallel_case infer_mux
		`SEL_00: begin
				regdata[7:0] = memdata[7:0];
			end
		`SEL_01: begin
				regdata[7:0] = memdata[15:8];
			end
		`SEL_10: begin
				regdata[7:0] = memdata[23:16];
			end
		`SEL_11: begin
				regdata[7:0] = memdata[31:24];
			end
	endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
	case(sel_byte1) // synopsys full_case parallel_case infer_mux
		`SEL_00: begin
				regdata[15:8] = 8'b0;
			end
		`SEL_01: begin
				regdata[15:8] = memdata[15:8];
			end
		`SEL_10: begin
				regdata[15:8] = {8{memdata[7]}};
			end
		`SEL_11: begin
				regdata[15:8] = memdata[31:24];
			end
	endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
	case(sel_byte2) // synopsys full_case parallel_case infer_mux
		`SEL_00: begin
				regdata[23:16] = 8'b0;
			end
		`SEL_01: begin
				regdata[23:16] = {8{memdata[7]}};
			end
		`SEL_10: begin
				regdata[23:16] = memdata[23:16];
			end
		`SEL_11: begin
				regdata[23:16] = {8{memdata[15]}};
			end
	endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
	case(sel_byte3) // synopsys full_case parallel_case infer_mux
		`SEL_00: begin
				regdata[31:24] = 8'b0;
			end
		`SEL_01: begin
				regdata[31:24] = {8{memdata[7]}};
			end
		`SEL_10: begin
				regdata[31:24] = {8{memdata[15]}};
			end
		`SEL_11: begin
				regdata[31:24] = memdata[31:24];
			end
	endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg	[width-1:0]		regdata;
reg	[width-1:0]		aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
	case(addr) // synopsys infer_mux
		2'b00:
			aligned = memdata;
		2'b01:
			aligned = {memdata[23:0], 8'b0};
		2'b10:
			aligned = {memdata[15:0], 16'b0};
		2'b11:
			aligned = {memdata[7:0], 24'b0};
	endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
	case(lsu_op) // synopsys infer_mux
		`LSUOP_LBZ: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = 24'b0;
			end
		`LSUOP_LBS: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = {24{aligned[31]}};
			end
		`LSUOP_LHZ: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = 16'b0;
			end
		`LSUOP_LHS: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = {16{aligned[31]}};
			end
		default:
				regdata = aligned;
	endcase
end
 
`endif
 
endmodule