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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module pic(
	// RISC Internal Interface
	clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
	pic_wakeup, int_low, int_high,
 
	// PIC Interface
	pic_int
);
 
//
// RISC Internal Interface
//
input		clk;		// Clock
input		rst;		// Reset
input		spr_cs;		// SPR CS
input		spr_write;	// SPR Write
input	[31:0]	spr_addr;	// SPR Address
input	[31:0]	spr_dat_i;	// SPR Write Data
output	[31:0]	spr_dat_o;	// SPR Read Data
output		pic_wakeup;	// Wakeup to the PM
output		int_low;	// Low priority interrupt
				// exception request
output		int_high;	// High priority interrupt
				// exception request
 
//
// PIC Interface
//
input	[`PIC_INTS-1:0]	pic_int;// Interrupt inputs
 
`ifdef PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef PIC_PICMR
reg	[`PIC_INTS-1:2]	picmr;	// PICMR bits
`else
wire	[`PIC_INTS-1:2]	picmr;	// No PICMR register
`endif
 
//
// PIC Priority Register bits (or no register)
//
`ifdef PIC_PICPR
reg	[`PIC_INTS-1:2]	picpr;	// PICPR bits
`else
wire	[`PIC_INTS-1:2]	picpr;	// No PICPR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef PIC_PICSR
reg	[`PIC_INTS-1:0]	picsr;	// PICSR bits
`else
wire	[`PIC_INTS-1:0]	picsr;	// No PICSR register
`endif
 
//
// Internal wires & regs
//
wire		picmr_sel;	// PICMR select
wire		picpr_sel;	// PICPR select
wire		picsr_sel;	// PICSR select
wire	[`PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg	[31:0] 	spr_dat_o;	// SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picpr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef PIC_PICMR
always @(posedge clk or posedge rst)
	if (rst)
//		picmr <= {`PIC_INTS-2{1'b0}};
		picmr <= {1'b1, {`PIC_INTS-3{1'b0}}};
	else if (picmr_sel && spr_write) begin
		picmr <= #1 spr_dat_i[`PIC_INTS-1:2];
	end
`else
assign picpr = (`PIC_INTS)'b1;
`endif
 
//
// Write to PICPR
//
`ifdef PIC_PICPR
always @(posedge clk or posedge rst)
	if (rst)
		picpr <= {`PIC_INTS-2{1'b0}};
	else if (picpr_sel && spr_write) begin
		picpr <= #1 spr_dat_i[`PIC_INTS-1:2];
	end
`else
assign picpr = 0;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef PIC_PICSR
always @(posedge clk or posedge rst)
	if (rst)
		picsr <= {`PIC_INTS-2{1'b0}};
	else if (picsr_sel && spr_write) begin
		picsr <= #1 spr_dat_i[`PIC_INTS-1:0] | um_ints;
	end else
		picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picpr or picsr)
	case (spr_addr[`PICOFS_BITS])	// synopsys full_case parallel_case
`ifdef PIC_READREGS
		`PIC_OFS_PICMR: begin
					spr_dat_o[`PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef PIC_UNUSED_ZERO
					spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
				end
		`PIC_OFS_PICPR: begin
					spr_dat_o[`PIC_INTS-1:0] = {picpr, 2'b0};
`ifdef PIC_UNUSED_ZERO
					spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
				end
`endif
		default: begin
				spr_dat_o[`PIC_INTS-1:0] = picsr;
`ifdef PIC_UNUSED_ZERO
				spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
			end
	endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate int_low
//
assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;
 
//
// Generate int_high
//
assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;
 
//
// Assert pic_wakeup when either intlow or int_high is asserted
//
assign pic_wakeup = int_low | int_high;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign int_low = pic_int[1];
assign int_high = pic_int[0];
assign pic_wakeup= int_low | int_high;
 
//
// Read PIC registers
//
`ifdef PIC_READREGS
assign spr_dat_o[`PIC_INTS-1:0] = `PIC_INTS'b0;
`ifdef PIC_UNUSED_ZERO
assign spr_dat_o[31:`PIC_INTS] = 32-`PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule