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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [sim/] [bin/] [nc.scr] - Rev 317
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+libext+.v +access+wr +overwrite +mess +tcl+../bin/sim.tcl +max_err_count+2 // // Test bench files // +incdir+../../bench/verilog ../../bench/verilog/xess_top.v ../../bench/verilog/or1200_monitor.v ../../bench/verilog/sram_init.v ../../bench/verilog/dbg_comm.v ../../bench/verilog/xcv_glbl.v // // Models // ../../bench/models/512Kx8.v ../../bench/models/vga_model.v ../../bench/models/codec_model.v +incdir+../../bench/models/28f016s3 ../../bench/models/28f016s3/bwsvff.v // // RTL files (top) // +incdir+../../rtl/verilog ../../rtl/verilog/xfpga_top.v ../../rtl/verilog/tcop_top.v // // RTL files (audio) // +incdir+../../rtl/verilog/audio ../../rtl/verilog/audio/audio_codec_if.v ../../rtl/verilog/audio/audio_top.v ../../rtl/verilog/audio/audio_wb_if.v ../../rtl/verilog/audio/fifo_4095_16.v ../../rtl/verilog/audio/fifo_empty_16.v // // RTL files (mem_if) // +incdir+../../rtl/verilog/mem_if ../../rtl/verilog/mem_if/flash_top.v ../../rtl/verilog/mem_if/sram_top.v // // RTL files (dbg_interface) // +incdir+../../rtl/verilog/dbg_interface ../../rtl/verilog/dbg_interface/dbg_crc8_d1.v ../../rtl/verilog/dbg_interface/dbg_defines.v ../../rtl/verilog/dbg_interface/dbg_register.v ../../rtl/verilog/dbg_interface/dbg_registers.v ../../rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v ../../rtl/verilog/dbg_interface/dbg_top.v ../../rtl/verilog/dbg_interface/dbg_trace.v // // RTL files (ssvga) // +incdir+../../rtl/verilog/ssvga ../../rtl/verilog/ssvga/crtc_iob.v ../../rtl/verilog/ssvga/ssvga_crtc.v ../../rtl/verilog/ssvga/ssvga_defines.v ../../rtl/verilog/ssvga/ssvga_fifo.v ../../rtl/verilog/ssvga/ssvga_top.v ../../rtl/verilog/ssvga/ssvga_wbm_if.v ../../rtl/verilog/ssvga/ssvga_wbs_if.v // // RTL files (or1200) // +incdir+../../rtl/verilog/or1200 ../../rtl/verilog/or1200/wb_biu.v ../../rtl/verilog/or1200/id.v ../../rtl/verilog/or1200/cpu.v ../../rtl/verilog/or1200/rf.v ../../rtl/verilog/or1200/alu.v ../../rtl/verilog/or1200/lsu.v ../../rtl/verilog/or1200/operandmuxes.v ../../rtl/verilog/or1200/wbmux.v ../../rtl/verilog/or1200/ifetch.v ../../rtl/verilog/or1200/frz_logic.v ../../rtl/verilog/or1200/sprs.v ../../rtl/verilog/or1200/or1200.v ../../rtl/verilog/or1200/pic.v ../../rtl/verilog/or1200/pm.v ../../rtl/verilog/or1200/tt.v ../../rtl/verilog/or1200/except.v ../../rtl/verilog/or1200/dc.v ../../rtl/verilog/or1200/dc_fsm.v ../../rtl/verilog/or1200/reg2mem.v ../../rtl/verilog/or1200/mem2reg.v ../../rtl/verilog/or1200/dc_tag.v ../../rtl/verilog/or1200/dc_ram.v ../../rtl/verilog/or1200/ic.v ../../rtl/verilog/or1200/ic_fsm.v ../../rtl/verilog/or1200/ic_tag.v ../../rtl/verilog/or1200/ic_ram.v ../../rtl/verilog/or1200/immu.v ../../rtl/verilog/or1200/itlb.v ../../rtl/verilog/or1200/dmmu.v ../../rtl/verilog/or1200/dtlb.v ../../rtl/verilog/or1200/generic_multp2_32x32.v ../../rtl/verilog/or1200/cfgr.v ../../rtl/verilog/or1200/du.v ../../rtl/verilog/or1200/mult_mac.v ../../rtl/verilog/or1200/generic_dpram_32x32.v ../../rtl/verilog/or1200/generic_spram_2048x32.v ../../rtl/verilog/or1200/generic_spram_2048x8.v ../../rtl/verilog/or1200/generic_spram_512x20.v ../../rtl/verilog/or1200/generic_spram_64x14.v ../../rtl/verilog/or1200/generic_spram_64x21.v ../../rtl/verilog/or1200/generic_spram_64x23.v ../../rtl/verilog/or1200/xcv_ram32x8d.v // // Library files // +incdir+../../lib/xilinx/coregen ../../lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v +incdir+../../lib/xilinx/unisims ../../lib/xilinx/unisims/RAMB4_S16.v ../../lib/xilinx/unisims/RAMB4_S4.v ../../lib/xilinx/unisims/RAMB4_S2.v ../../lib/xilinx/unisims/RAMB4_S16_S16.v ../../lib/xilinx/unisims/RAM32X1D.v ../../lib/xilinx/unisims/RAMB4_S8_S16.v ../../lib/xilinx/unisims/IBUFG.v ../../lib/xilinx/unisims/BUFG.v ../../lib/xilinx/unisims/CLKDLL.v
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