Subversion Repositories or1k

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input				clk;
input				rst;
input	[width-1:0]		a;
input	[width-1:0]		b;
input	[width-1:0]		mult_mac_result;
input				macrc_op;
input	[`ALUOP_WIDTH-1:0]	alu_op;
input	[`SHROTOP_WIDTH-1:0]	shrot_op;
input	[`COMPOP_WIDTH-1:0]	comp_op;
output	[width-1:0]		result;
output				flag;
 
//
// Internal wires and regs
//
reg	[width-1:0]		result;
reg	[width-1:0]		shifted_rotated;
reg				flagforw;
reg				flag_we;
reg				flag;
integer				d1;
integer				d2;
wire	[width-1:0]		comp_a;
wire	[width-1:0]		comp_b;
wire				a_eq_b;
wire				a_lt_b;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
	if (result === 32'bx)
		$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
	casex (alu_op)		// synopsys parallel_case full_case
		`ALUOP_SHROT : begin 
				result = shifted_rotated;
				flag_we = 1'b0;
		end
		`ALUOP_ADD : begin
				result = a + b;
				flag_we = 1'b0;
		end
		`ALUOP_SUB : begin
				result = a - b;
				flag_we = 1'b0;
		end
		`ALUOP_XOR : begin
				result = a ^ b;
				flag_we = 1'b0;
		end
		`ALUOP_OR  : begin
				result = a | b;
				flag_we = 1'b0;
		end
		`ALUOP_IMM : begin
				result = b;
				flag_we = 1'b0;
		end
		`ALUOP_MOVHI : begin
				if (macrc_op) begin
					result = mult_mac_result;
					flag_we = 1'b0;
				end
				else begin
					result = b << 16;
					flag_we = 1'b0;
				end
		end
		`ALUOP_MUL : begin
				result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
				flag_we = 1'b0;
		end
// synopsys translate_off
`ifdef SIM_ALU_DIV
		`ALUOP_DIV : begin
				d1 = a;
				d2 = b;
				$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
				if (d2)
					result = d1 / d2;
				else
					result = 32'h00000000;
				flag_we = 1'b0;
		end
`endif
`ifdef SIM_ALU_DIVU
		`ALUOP_DIVU : begin
				if (b)
					result = a / b;
				else
					result = 32'h00000000;
				flag_we = 1'b0;
		end
`endif
// synopsys translate_on
		`ALUOP_COMP: begin
				flag_we = 1'b1;
				result = 32'd0;
		end
		default : begin	// `ALUOP_AND
				result = a & b;
				flag_we = 1'b0;
		end
	endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
	case (shrot_op)		// synopsys parallel_case
		`SHROTOP_SLL :
				shifted_rotated = (a << b[4:0]);
		`SHROTOP_SRL :
				shifted_rotated = (a >> b[4:0]);
`ifdef IMPL_ALU_ROTATE
		`SHROTOP_ROR :
				shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
		default:
				shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
	endcase
end
 
//
// First type of compare implementation
//
`ifdef IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
	case(comp_op[2:0])	// synopsys parallel_case
		`COP_SFEQ:
			flagforw = a_eq_b;
		`COP_SFNE:
			flagforw = ~a_eq_b;
		`COP_SFGT:
			flagforw = ~(a_eq_b | a_lt_b);
		`COP_SFGE:
			flagforw = ~a_lt_b;
		`COP_SFLT:
			flagforw = a_lt_b;
		`COP_SFLE:
			flagforw = a_eq_b | a_lt_b;
// synopsys translate_off
		default:
			flagforw = 1'bx;
// synopsys translate_on
	endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef IMPL_ALU_COMP2
always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin
	case(comp_op[2:0])	// synopsys parallel_case
		`COP_SFEQ:
			flagforw = (comp_a == comp_b);
		`COP_SFNE:
			flagforw = (comp_a != comp_b);
		`COP_SFGT:
			flagforw = (comp_a > comp_b);
		`COP_SFGE:
			flagforw = (comp_a >= comp_b);
		`COP_SFLT:
			flagforw = (comp_a < comp_b);
		`COP_SFLE:
			flagforw = (comp_a <= comp_b);
// synopsys translate_off
		default:
			flagforw = 1'bx;
// synopsys translate_on
	endcase
end
`endif
 
//
// Flag bit
//
always @(posedge clk or posedge rst) begin
	if (rst)
		flag <= #1 1'b0;
	else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
		$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
// synopsys translate_on
`endif
		flag <= #1 flagforw;
	end
end
 
endmodule