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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data Cache top level                               ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DC blocks.                             ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
// Data cache
 
module dc(clk, rst, clkdiv_by_2, dcbiu_rdy, dclsu_addr, dclsu_lsuop, dclsu_datain, dcbiu_datain,
	dclsu_dataout, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dclsu_stall,
	tp2w, tp3w, tpdw
);
 
parameter dw = `OPERAND_WIDTH;
 
input clk;
input rst;
input clkdiv_by_2;
input dcbiu_rdy;
input [31:0] dclsu_addr;
input [`LSUOP_WIDTH-1:0] dclsu_lsuop;
input [dw-1:0] dclsu_datain;
input [dw-1:0] dcbiu_datain;
 
output [dw-1:0] dclsu_dataout;
output [dw-1:0] dcbiu_dataout;
output [31:0] dcbiu_addr;
output dcbiu_read;
output dcbiu_write;
output dclsu_stall;
 
input [`TP2W_WIDTH-1:0] tp2w;
input [`TP3W_WIDTH-1:0] tp3w;
input [31:0] tpdw;
 
wire [18:0] tag;
wire [dw-1:0] to_dcram;
wire [dw-1:0] from_dcram;
wire [dw-1:0] to_mem2reg;
wire [31:0] saved_addr;
wire refill;
wire [3:0] dcram_we;
wire dctag_we;
wire [dw-1:0] lsu_datain_memaligned;
wire [31:0] dc_addr;
wire refill_first;
wire refill_prepare;
wire refill_start;
wire refill_rest;
 
reg hit;
reg [1:0] valid_div;
 
wire queue;
wire cntrbusy;
wire dcbiu_valid;
 
assign dcbiu_addr = dc_addr;
assign dctag_we = refill;
assign dcbiu_dataout = from_dcram;
 
// assign dc_stall = dcbiu_read | dcbiu_write | refill_start;  // can't remember if it works
assign queue = (refill && dclsu_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
 
// assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue;  // kind of working
assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy;
 
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
 
// Select between input data generated by LSU or by BIU
assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
 
// Select between data generated by DCRAM or passed by BIU
assign to_mem2reg = (refill_first == 1'b1) ? dcbiu_datain : from_dcram;
 
// Tag comparison
always @(tag or saved_addr) begin
	if (tag == saved_addr[31:13])
		hit <= #1 1'b1;
	else
		hit <= #1 1'b0;
end
 
// Valid_div counts RISC clock cycles by modulo 4
always @(posedge clk or posedge rst)
        if (rst)
                valid_div <= #1 2'b0;
        else
                valid_div <= #1 valid_div + 'd1;
 
// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.
// dcbiu_rdy is two or four RISC clock cycles long because memory
// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if
// clkdiv_by_2 is asserted).
assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0];
 
// Generate refill_start that signals to frz_logic a cache linefill is about to begin
assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;
 
dtlb dtlb(
        .clk(clk),
        .rst(rst),
        .we(1'b0),
        .tlb_en(1'b1),
        .datain(dclsu_datain),
        .vaddr(saved_addr),
        .paddr(),
        .cache_en(),
        .tlb_miss(),
	.tp3w(tp3w),
	.tpdw(tpdw)
);
 
dc_fsm dc_fsm(
	.clk(clk),
	.rst(rst),
	.lsu_op(dclsu_lsuop),
	.miss(~hit),
	.biudata_valid(dcbiu_valid),
	.start_addr(dclsu_addr),
	.saved_addr(saved_addr),
	.refill(refill),
	.refill_first(refill_first),
	.refill_prepare(refill_prepare),
	.dcram_we(dcram_we),
	.biu_read(dcbiu_read),
	.biu_write(dcbiu_write),
	.refill_rest(refill_rest),
	.cntrbusy(cntrbusy)
);
 
// Regfile-to-memory aligner
reg2mem reg2mem(
	.addr(dc_addr[1:0]),
	.lsu_op(dclsu_lsuop),
	.regdata(dclsu_datain),
	.memdata(lsu_datain_memaligned)
);
 
dc_ram dc_ram(
	.clk(clk),
	.addr(dc_addr[12:2]),
	.we(dcram_we),
	.datain(to_dcram),
	.dataout(from_dcram),
	.tp2w(tp2w),
	.tpdw(tpdw)
);
 
dc_tag dc_tag(
	.clk(clk),
	.addr(dc_addr[12:4]),
	.we(dctag_we),
	.datain(dc_addr[31:13]),
	.dataout(tag),
	.tp2w(tp2w),
	.tpdw(tpdw)
);
 
// Memory-to-regfile aligner
mem2reg mem2reg(
	.addr(saved_addr[1:0]),
	.lsu_op(dclsu_lsuop),
	.memdata(to_mem2reg),
	.regdata(dclsu_dataout)
);
 
endmodule