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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc_tag.v] - Rev 161
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's DC TAG RAMs //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instatiation of data cache tag rams. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // `include "general.h" `define NO_UTI module dc_tag(clk, addr, we, datain, dataout, tp2w, tpdw); parameter dw = 19; parameter aw = 9; input [dw-1:0] datain; output [dw-1:0] dataout; input [aw-1:0] addr; input we; input clk; input [`TP2W_WIDTH-1:0] tp2w; input [31:0] tpdw; wire high, low; assign high = 1; assign low = 0; `ifdef NO_UTI art_hssp_512x19 dc_tag0( .q(dataout), .clk(clk), .cen(low), .oen(low), .wen(~we), .a(addr), .d(datain) ); `else art_hssp_512x19 dc_tag0( .q(dataout), .censq(), .oensq(), .wensq(), .asq(), .tq(), .clk(clk), .cen(low), .oen(low), .wen(~we), .a(addr), .d(datain), .tis(tp2w[`TP2W_DCT_TIS]), .tms(tp2w[`TP2W_DCT_TMS]), .tcen(tp2w[`TP2W_DCT_TCEN]), //normally high .toen(tp2w[`TP2W_DCT_TOEN]), .tqoen(tp2w[`TP2W_DCT_TQOEN]), .twen(tp2w[`TP2W_DCT_TWEN]), .ta(tp2w[`TP2W_DCT_TA]), .td(tpdw[dw-1:0]) ); `endif endmodule
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