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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data TLB                                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of DTLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Data TLB
//
 
module dtlb(
	// Rst and clk
	clk, rst,
 
	// I/F for translation
	tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre,
 
	// SPR access
	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input				clk;
input				rst;
 
//
// I/F for translation
//
input				tlb_en;
input	[aw-1:0]		vaddr;
output				hit;
output	[31:13]			ppn;
output				uwe;
output				ure;
output				swe;
output				sre;
 
//
// SPR access
//
input				spr_cs;
input				spr_write;
input	[31:0]			spr_addr;
input	[31:0]			spr_dat_i;
output	[31:0]			spr_dat_o;
 
//
// Internal wires and regs
//
wire	[31:19]			vpn;
wire				v;
wire	[5:0]			tlb_index;
wire				tlb_mr_en;
wire				tlb_mr_we;
wire	[13:0]			tlb_mr_ram_in;
wire	[13:0]			tlb_mr_ram_out;
wire				tlb_tr_en;
wire				tlb_tr_we;
wire	[22:0]			tlb_tr_ram_in;
wire	[22:0]			tlb_tr_ram_out;
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19  v 0
// dtlbwYtrX: ppn 31-13  uwe 9  ure 8  swe 7  sre 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[9]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[9]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[9];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ?
			{vpn, {18{1'b1}}, v} :
		(spr_cs & !spr_write & spr_addr[9]) ?
			{ppn, 3'b000, uwe, ure, swe, sre, {6{1'b1}}} :
			32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, uwe, ure, swe, sre} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[9:6]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[31:19]) & v;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13];
 
//
// Instantiation of DTLB Match Registers
//
generic_spram_64x14 dtlb_mr_ram(
	.clk(clk),
	.rst(rst),
	.ce(tlb_mr_en),
	.we(tlb_mr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_mr_ram_in),
	.do(tlb_mr_ram_out)
);
 
//
// Instantiation of DTLB Translate Registers
//
generic_spram_64x23 dtlb_tr_ram(
	.clk(clk),
	.rst(rst),
	.ce(tlb_tr_en),
	.we(tlb_tr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_tr_ram_in),
	.do(tlb_tr_ram_out)
);
 
endmodule