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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Debug unit
//
 
module du(
	// RISC Internal Interface
	clk, rst,
	du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write,
	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
	dclsu_lsuop, icfetch_op,
 
	// External Debug Interface
	dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input				clk;		// Clock
input				rst;		// Reset
output				du_stall;	// Debug Unit Stall
output	[aw-1:0]		du_addr;	// Debug Unit Address
input	[dw-1:0]		du_dat_i;	// Debug Unit Data In
output	[dw-1:0]		du_dat_o;	// Debug Unit Data Out
output				du_read;	// Debug Unit Read Enable
output				du_write;	// Debug Unit Write Enable
input				spr_cs;		// SPR Chip Select
input				spr_write;	// SPR Read/Write
input	[aw-1:0]		spr_addr;	// SPR Address
input	[dw-1:0]		spr_dat_i;	// SPR Data Input
output	[dw-1:0]		spr_dat_o;	// SPR Data Output
input	[`LSUOP_WIDTH-1:0]	dclsu_lsuop;	// LSU status
input	[`FETCHOP_WIDTH-1:0]	icfetch_op;	// IFETCH unit status
 
//
// External Debug Interface
//
input				dbg_stall_i;	// External Stall Input
input	[dw-1:0]		dbg_dat_i;	// External Data Input
input	[aw-1:0]		dbg_adr_i;	// External Address Input
input	[2:0]			dbg_op_i;	// External Operation Select Input
input				dbg_ewt_i;	// External Watchpoint Trigger Input
output	[3:0]			dbg_lss_o;	// External Load/Store Unit Status
output	[1:0]			dbg_is_o;	// External Insn Fetch Status
output	[10:0]			dbg_wp_o;	// Watchpoints Outputs
output				dbg_bp_o;	// Breakpoint Output
output	[dw-1:0]		dbg_dat_o;	// External Data Output
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dclsu_lsuop;
assign dbg_is_o = icfetch_op;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
 
`ifdef DU_IMPLEMENTED
 
//
// Power Management Register bits
//
reg	[3:0]	sdf;	// Slow-down factor
reg		dme;	// Doze Mode Enable
reg		sme;	// Sleep Mode Enable
reg		dcge;	// Dynamic Clock Gating Enable
 
//
// Internal wires
//
wire		pmr_sel; // PMR select
wire		pmr_we;	 // PMR write
 
//
// PMR address decoder (partial decoder)
//
`ifdef DU_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`SPRGRP_BITS] == `SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`SPRGRP_BITS] == `SPRGRP_PM) &&
		  (spr_addr[`SPROFS_BITS] == `PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
 
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
	if (rst)
		{dcge, sme, dme, sdf} <= 7'b0;
	else if (pmr_sel && pmr_we) begin
		sdf <= #1 spr_dat_i[`PM_PMR_SDF];
		dme <= #1 spr_dat_i[`PM_PMR_DME];
		sme <= #1 spr_dat_i[`PM_PMR_SME];
		dcge <= #1 spr_dat_i[`PM_PMR_DCGE];
	end
	else if (pic_wakeup) begin
		dme <= #1 1'b0;
		sme <= #1 1'b0;
	end
 
//
// Read PMR
//
`ifdef DU_READREGS
assign spr_dat_o[`PM_PMR_SDF] = sdf;
assign spr_dat_o[`PM_PMR_DME] = dme;
assign spr_dat_o[`PM_PMR_SME] = sme;
assign spr_dat_o[`PM_PMR_DCGE] = dcge;
`ifdef DU_UNUSED_ZERO
assign spr_dat_o[`PM_PMR_UNUSED] = 25'b0;
`endif
`endif
 
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
 
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
 
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
 
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
assign pm_lvolt = pm_cpu_gate | pm_cpustall;
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_bp_o = 1'b0;
assign dbg_dat_o = du_dat_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `DU_OP_READSPR);
assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
 
//
// Read PMR
//
`ifdef DU_READREGS
assign spr_dat_o = 32'b0;
`ifdef DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule