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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
`define NO_FREEZE	3'd0
`define FREEZE_BYDC	3'd1
`define FREEZE_BYMULTICYCLE	3'd2
`define WAIT_LSU_TO_FINISH	3'd3
`define WAIT_IC			3'd4
 
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
 
module frz_logic(clk, rst, multicycle, except_flushpipe, lsu_stall, ic_stall, branch_stall, pipeline_freeze);
 
input clk;
input rst;
input [`MULTICYCLE_WIDTH-1:0] multicycle;
input except_flushpipe;
input lsu_stall;
input ic_stall;
input branch_stall;
output pipeline_freeze;
 
reg multicycle_freeze;
reg [1:0] state;
reg [2:0] state2;
reg [2:0] multicycle_cnt;
reg done_once;
 
assign pipeline_freeze = (lsu_stall | (ic_stall) | multicycle_freeze) & ~except_flushpipe;
 
//always @(lsu_stall or multicycle or multicycle or multicycle_cnt) begin
always @(posedge clk or posedge rst) begin
	if (rst) begin
                state <= #1 `NO_FREEZE;
	end
	else
		case (state)	// synopsys full_case parallel_case
		`NO_FREEZE :
			if (lsu_stall) begin
				state <= #1 `FREEZE_BYDC; 
			end
		`FREEZE_BYDC :
			if (!lsu_stall) begin
				state <= #1 `NO_FREEZE;
			end
	endcase
end
 
always @(posedge clk or posedge rst) begin
	if (rst) begin
                state2 <= #1 `NO_FREEZE;
		multicycle_freeze <= #1 1'b1;
		multicycle_cnt <= #1 3'b0;
		done_once <= #1 1'b0;
	end
	else
		case (state2)	// synopsys full_case parallel_case
		`NO_FREEZE :
			if (done_once && pipeline_freeze)
				done_once <= #1 1'b1;
			else if (multicycle) begin
				state2 <= #1 `FREEZE_BYMULTICYCLE;
				multicycle_freeze <= #1 1'b1;
				multicycle_cnt <= #1 multicycle - 'd1;
				done_once <= #1 1'b0;
			end
			else
				multicycle_freeze <= #1 1'b0;
		`FREEZE_BYMULTICYCLE :
			if (multicycle_cnt) begin
				multicycle_cnt <= #1 multicycle_cnt - 'd1;
				state2 <= #1 `FREEZE_BYMULTICYCLE;
			end
			else if (lsu_stall) begin
				state2 <= #1 `WAIT_LSU_TO_FINISH;
				multicycle_freeze <= #1 1'b0;
			end
			else if (ic_stall) begin
				state2 <= #1 `NO_FREEZE;
				done_once <= #1 1'b1;
				multicycle_freeze <= #1 1'b0;
			end
			else begin
				state2 <= #1 `NO_FREEZE;
				multicycle_freeze <= #1 1'b0;
			end
		`WAIT_LSU_TO_FINISH:
			if (!lsu_stall && !multicycle) begin
				state2 <= #1 `NO_FREEZE;
			end
			else if (!lsu_stall && multicycle) begin
				state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
			end
	endcase
end
 
endmodule