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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define NO_FREEZE	3'd0
`define FREEZE_BYDC	3'd1
`define FREEZE_BYMULTICYCLE	3'd2
`define WAIT_LSU_TO_FINISH	3'd3
`define WAIT_IC			3'd4
 
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module frz_logic(
	// Clock and reset
	clk, rst,
 
	// Internal i/f
	multicycle, except_flushpipe, lsu_stall, if_stall,
	dclsu_unstall, branch_stall, du_stall, mac_stall, 
	force_dslot_fetch,
	if_freeze, id_freeze, ex_freeze, wb_freeze
);
 
//
// I/O
//
input				clk;
input				rst;
input	[`MULTICYCLE_WIDTH-1:0]	multicycle;
input				except_flushpipe;
input				lsu_stall;
input				if_stall;
input				dclsu_unstall;
input				branch_stall;
input				force_dslot_fetch;
input				du_stall;
input				mac_stall;
output				if_freeze;
output				id_freeze;
output				ex_freeze;
output				wb_freeze;
 
//
// Internal wires and regs
//
reg				multicycle_freeze;
reg	[2:0]			state2;
reg	[2:0]			multicycle_cnt;
reg				done_once;
 
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign if_freeze = id_freeze;
assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe | du_stall;
assign ex_freeze = wb_freeze;
assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe | du_stall | mac_stall;
 
//
// Freeze FSM2
//
always @(posedge clk or posedge rst) begin
	if (rst) begin
                state2 <= #1 `NO_FREEZE;
		multicycle_freeze <= #1 1'b1;
		multicycle_cnt <= #1 3'b0;
		done_once <= #1 1'b0;
	end
	else
		case (state2)	// synopsys parallel_case
		`NO_FREEZE :
			if (done_once && ex_freeze)
				done_once <= #1 1'b1;
			else if (multicycle) begin
				state2 <= #1 `FREEZE_BYMULTICYCLE;
				multicycle_freeze <= #1 1'b1;
				multicycle_cnt <= #1 multicycle - 'd1;
				done_once <= #1 1'b0;
			end
			else
				multicycle_freeze <= #1 1'b0;
		`FREEZE_BYMULTICYCLE :
			if (multicycle_cnt) begin
				multicycle_cnt <= #1 multicycle_cnt - 'd1;
				state2 <= #1 `FREEZE_BYMULTICYCLE;
			end
			else if (lsu_stall) begin
				state2 <= #1 `WAIT_LSU_TO_FINISH;
				multicycle_freeze <= #1 1'b0;
			end
			else if (if_stall) begin
				state2 <= #1 `NO_FREEZE;
				done_once <= #1 1'b1;
				multicycle_freeze <= #1 1'b0;
			end
			else begin
				state2 <= #1 `NO_FREEZE;
				multicycle_freeze <= #1 1'b0;
			end
		`WAIT_LSU_TO_FINISH:
			if (!lsu_stall && !(|multicycle)) begin
				state2 <= #1 `NO_FREEZE;
			end
			else if (!lsu_stall & (|multicycle)) begin
				state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
			end
	endcase
end
 
endmodule