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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [ic_ram.v] - Rev 168
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's IC RAMs //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instantiation of Instruction cache data rams //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.2 2001/07/22 03:31:54 lampret // Fixed RAM's oen bug. Cache bypass under development. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // `include "timescale.v" `include "defines.v" module ic_ram( // Clock and reset clk, rst, // Internal i/f addr, we, datain, dataout ); parameter dw = `OPERAND_WIDTH; parameter aw = `ICINDX; // // I/O // input clk; input rst; input [aw-1:0] addr; input [3:0] we; input [dw-1:0] datain; output [dw-1:0] dataout; // // Instantiation of 2048x32 RAM block // generic_spram_2048x32 ic_ram0( .clk(clk), .rst(rst), .ce(1'b1), .we(we[0]), .oe(1'b1), .addr(addr), .di(datain), .do(dataout) ); endmodule
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