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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module ifetch(
	// Clock and reset
	clk, rst,
 
	// External i/f to IC
	ic_insn, ic_addr, ic_stall, ic_fetchop,
 
	// Internal i/f
	if_freeze, if_insn, if_pc, branch_op, except_type,
	branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,
	epcr, force_dslot_fetch, if_stall, branch_stall,
	spr_dat_i, spr_pc_we
);
 
//
// I/O
//
 
//
// Clock and reset
//
input				clk;
input				rst;
 
//
// External i/f to IC
//
input	[31:0]			ic_insn;
output	[31:0]			ic_addr;
output	[`FETCHOP_WIDTH-1:0]	ic_fetchop;
input				ic_stall;
 
//
// Internal i/f
//
input				if_freeze;
output	[31:0]			if_insn;
output	[31:0]			if_pc;
input	[`BRANCHOP_WIDTH-1:0]	branch_op;
input	[`EXCEPT_WIDTH-1:0]	except_type;
input	[31:2]			branch_addrofs;
input	[31:0]			lr_restor;
input				flag;
input	[31:2]			binsn_addr;
output				taken;
input				except_start;
input	[31:0]			epcr;
input				force_dslot_fetch;
output				if_stall;
output				branch_stall;
input	[31:0]			spr_dat_i;
input				spr_pc_we;
 
//
// Internal wires and regs
//
reg	[31:2]			pcreg;
reg	[32:2]			dslot_pc;
reg	[32:0]			if_saved;
reg	[31:0]			pcaddr;
reg	[31:0]			pc_saved;
reg				taken;	/* Set to in case of jump or taken branch */
 
//
// Current registered PC (corresponds to fetched instruction)
//
//assign if_pc = {pcreg[31:2], 2'b00};
assign if_pc = (if_saved[32]) ? pc_saved : ic_addr;
assign ic_addr = dslot_pc[32] ? {dslot_pc[31:2], 2'b00} : pcaddr;
assign branch_stall = dslot_pc[32] & taken;
//assign if_stall = ic_stall | (~branch_stall & taken);
assign if_stall = ic_stall;
 
//
// Control access to IC subsystem
//
assign ic_fetchop = (if_saved[32] & !if_stall) ? `FETCHOP_NOP : `FETCHOP_LW;
 
//
// Just fetched instruction
//
assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall) ? 32'h1500FFFF : ic_insn;
 
//
// Delay slot PC saved
//
always @(posedge clk or posedge rst)
	if (rst)
		dslot_pc <= #1 31'h00000000;
//	else if (force_dslot_fetch)
//		dslot_pc <= #1 {1'b1, pcaddr[31:2]};
	else if (!ic_stall)
		dslot_pc <= #1 31'h00000000;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
	or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin
	casex ({spr_pc_we, except_start, branch_op})	// synopsys parallel_case
		{2'b00, `BRANCHOP_NOP}: begin
			pcaddr = {pcreg + 'd1, 2'b0};
			taken = 1'b0;
		end
		{2'b00, `BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_J: pcaddr <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
			pcaddr = {branch_addrofs, 2'b0};
			taken = 1'b1;
		end
		{2'b00, `BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_JR: pcaddr <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
			pcaddr = lr_restor;
			taken = 1'b1;
		end
		{2'b00, `BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_BAL: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
			pcaddr = {binsn_addr + branch_addrofs, 2'b0};
			taken = 1'b1;
		end
		{2'b00, `BRANCHOP_BF}:
			if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BF: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
				pcaddr = {binsn_addr + branch_addrofs, 2'b0};
				taken = 1'b1;
			end
			else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
				pcaddr = {pcreg + 'd1, 2'b0};
				taken = 1'b0;
			end
		{2'b00, `BRANCHOP_BNF}:
			if (flag) begin
				pcaddr = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
				taken = 1'b0;
			end
			else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BNF: pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
				pcaddr = {binsn_addr + branch_addrofs, 2'b0};
				taken = 1'b1;
			end
		{2'b00, `BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_RFE: pcaddr <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
			pcaddr = epcr;
			taken = 1'b1;
		end
		{2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
			pcaddr = { 20'h0_0000, except_type, 8'h00};
			taken = 1'b1;
		end
		default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
			pcaddr = spr_dat_i;
			taken = 1'b0;
		end
	endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst) begin
	if (rst)
		pcreg <= #1 30'd64;
	else if (spr_pc_we)
		pcreg <= #1 spr_dat_i[31:2];
	else if (!if_freeze && !ic_stall) begin
		pcreg <= #1 ic_addr[31:2];
`ifdef OR1200_VERBOSE
// synopsys translate_off
		$display("%t: pcreg incremented to %h", $time, {ic_addr[31:2], 2'b0});
// synopsys translate_on
`endif
	end
end
 
//
// Stores INSN when pipeline is frozen
//
always @(posedge clk or posedge rst)
	if (rst) begin
		if_saved <= #1 33'b0;
	end
	else if (if_freeze && !if_saved[32] && !ic_stall) begin  // && !taken
		if_saved <= #1 {1'b1, ic_insn};
`ifdef OR1200_VERBOSE
// synopsys translate_off
		$display("%t: if_saved <= %h", $time, {1'b1, ic_insn});
// synopsys translate_on
`endif
	end
	else if (!if_freeze) begin
		if_saved[32] <= #1 1'b0;
		if_saved[31:0] <= #1 32'h1500eeee;
`ifdef OR1200_VERBOSE
// synopsys translate_off
		$display("%t: if_saved[32] <= 0", $time);
// synopsys translate_on
`endif
	end
 
//
// Stores PC when pipeline is frozen
//
always @(posedge clk or posedge rst)
	if (rst) begin
		pc_saved <= #1 32'b0;
	end
	else if (if_freeze && !if_saved[32] && !ic_stall) begin  // && !taken
		pc_saved <= #1 ic_addr;
	end
	else if (!if_freeze) begin
		pc_saved <= #1 32'h00000000;
	end
 
endmodule