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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
//`define XCV_RF
`define ART_DP
 
module rf(clk, rst, addrw, dataw, pipeline_freeze, we, addra, dataa, addrb, datab,
	rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w, tpdw
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
input clk, rst, pipeline_freeze, we;
 
input [dw-1:0] dataw;
output [dw-1:0] dataa;
output [dw-1:0] datab;
 
input [aw-1:0] addrw;
input [aw-1:0] addra;
input [aw-1:0] addrb;
 
// Trace port
output [31:0] rfa_tqa;
output [31:0] rfb_tqa;
output [`TP1R_WIDTH-1:0] rfa_tmuxed;
output [`TP1R_WIDTH-1:0] rfb_tmuxed;
input [`TP1W_WIDTH-1:0] tp1w;
input [31:0] tpdw;
 
wire [dw-1:0] from_rfa, from_rfb;
 
wire [dw-1:0] t_dataw; // for test port
wire [aw-1:0] t_addrw; // for test port
wire [aw-1:0] t_addra; // for test port
wire [aw-1:0] t_addrb; // for test port
 
reg [dw:0] dataa_saved, datab_saved;
 
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
// Stores operand from RF_A into temp reg when pipeline is frozen
always @(posedge clk or posedge rst)
	if (rst) begin
		dataa_saved <= #1 33'b0;
	end
	else if (pipeline_freeze & !dataa_saved[32]) begin
		dataa_saved <= #1 {1'b1, from_rfa};
	end
	else if (!pipeline_freeze)
		dataa_saved[32] <= #1 1'b0;
 
// Stores operand from RF_B into temp reg when pipeline is frozen
always @(posedge clk or posedge rst)
	if (rst) begin
		datab_saved <= #1 33'b0;
	end
	else if (pipeline_freeze & !datab_saved[32]) begin
		datab_saved <= #1 {1'b1, from_rfb};
	end
	else if (!pipeline_freeze)
		datab_saved[32] <= #1 1'b0;
 
`ifdef XCV_RF
// Instantiation of register file memory (A)
xcv_rfram rf(
	.clk(clk),
	.rst(rst),
	.we(we),
	.addrw(addrw),
	.dataw(dataw),
	.addra(addra),
	.dataa(from_rfa),
	.addrb(addrb),
	.datab(from_rfb)
);
 
`else
 
`ifdef ART_DP
// Instatiation of dual port high density artisan sram memory
art_hsdp_32x32 rf_a(
   .qa(from_rfa),
   .clka(clk),
   .cena(1'b0),
   .wena(1'b1),
   .aa(addra),
   .da(32'b0),
   .oena(1'b0),
   .qb(),
   .clkb(clk),
   .cenb(1'b0),
   .wenb(1'b0),
   .ab(addrw),
   .db(dataw),
   .oenb(1'b1)
);
 
art_hsdp_32x32 rf_b(
   .qa(from_rfb),
   .clka(clk),
   .cena(1'b0),
   .wena(1'b1),
   .aa(addrb),
   .da(32'b0),
   .oena(1'b0),
   .qb(),
   .clkb(clk),
   .cenb(1'b0),
   .wenb(1'b0),
   .ab(addrw),
   .db(dataw),
   .oenb(1'b1)
);
 
assign rfa_tqa = 32'b0;
assign rfb_tqa = 32'b0;
assign rfa_tmuxed = `TP1R_WIDTH'b0;
assign rfb_tmuxed = `TP1R_WIDTH'b0;
 
`else
 
// Instantiation of register file memory (A)
art_rf2r_32x32 rf_a(
	.QA(from_rfa),
 
	.OENSQA(rfa_tmuxed[`TP1R_RF_OENSQA]),
	.ASQA(rfa_tmuxed[`TP1R_RF_ASQA]),
	.TQA(rfa_tqa),
	.QSQA(rfa_tmuxed[`TP1R_RF_QSQA]),
	.DSOB(rfa_tmuxed[`TP1R_RF_DSOB]),
	.CENSQB(rfa_tmuxed[`TP1R_RF_CENSQB]),
	.ASQB(rfa_tmuxed[`TP1R_RF_ASQB]),
 
	.CLKA(clk),
	.CENA(1'b0),
	.OENA(1'b0),
	.AA(addra),
	.TISA(tp1w[`TP1W_RF_TISA]),
	.TMSA(tp1w[`TP1W_RF_TMSA]),
	.TCENA(tp1w[`TP1W_RF_TCENA]),
	.TOENA(tp1w[`TP1W_RF_TOENA]),
	.TQOENA(tp1w[`TP1W_RF_TQOENA]),
	.TAA(tp1w[`TP1W_RF_TAA]),
	.CLKB(clk),
	.CENB(~we),
	.AB(addrw),
	.DB(dataw),
	.TISB(tp1w[`TP1W_RF_TISB]),
	.TMSB(tp1w[`TP1W_RF_TMSB]),
	.TCENB(tp1w[`TP1W_RF_TCENB]),
	.TAB(tp1w[`TP1W_RF_TAB]),
	.TDB(tpdw),
	.SMSB(tp1w[`TP1W_RF_SMSB]),
	.DSIB(tp1w[`TP1W_RF_DSIB])
);
 
// Instantiation of register file memory (B)
art_rf2r_32x32 rf_b(
	.QA(from_rfb),
 
	.OENSQA(rfb_tmuxed[`TP1R_RF_OENSQA]),
	.ASQA(rfb_tmuxed[`TP1R_RF_ASQA]),
	.TQA(rfb_tqa),
	.QSQA(rfb_tmuxed[`TP1R_RF_QSQA]),
	.DSOB(rfb_tmuxed[`TP1R_RF_DSOB]),
	.CENSQB(rfb_tmuxed[`TP1R_RF_CENSQB]),
	.ASQB(rfb_tmuxed[`TP1R_RF_ASQB]),
 
	.CLKA(clk),
	.CENA(1'b0),
	.OENA(1'b0),
	.AA(addrb),
	.TISA(tp1w[`TP1W_RF_TISA]),
	.TMSA(tp1w[`TP1W_RF_TMSA]),
	.TCENA(tp1w[`TP1W_RF_TCENA]),
	.TOENA(tp1w[`TP1W_RF_TOENA]),
	.TQOENA(tp1w[`TP1W_RF_TQOENA]),
	.TAA(tp1w[`TP1W_RF_TAA]),
	.CLKB(clk),
	.CENB(~we),
	.AB(addrw),
	.DB(dataw),
	.TISB(tp1w[`TP1W_RF_TISB]),
	.TMSB(tp1w[`TP1W_RF_TMSB]),
	.TCENB(tp1w[`TP1W_RF_TCENB]),
	.TAB(tp1w[`TP1W_RF_TAB]),
	.TDB(tpdw),
	.SMSB(tp1w[`TP1W_RF_SMSB]),
	.DSIB(tp1w[`TP1W_RF_DSIB])
);
`endif
`endif
/*
art_rf2r_32x32 rf_a(
	.qa(from_rfa),
 
	.oensqa(rfa_tmuxed[`TP1R_RF_OENSQA]),
	.asqa(rfa_tmuxed[`TP1R_RF_ASQA]),
	.tqa(rfa_tqa),
	.qsqa(rfa_tmuxed[`TP1R_RF_QSQA]),
	.dsob(rfa_tmuxed[`TP1R_RF_DSOB]),
	.censqb(rfa_tmuxed[`TP1R_RF_CENSQB]),
	.asqb(rfa_tmuxed[`TP1R_RF_ASQB]),
 
	.clka(clk),
	.cena(1'b0),
	.oena(1'b0),
	.aa(addra),
	.tisa(tp1w[`TP1W_RF_TISA]),
	.tmsa(tp1w[`TP1W_RF_TMSA]),
	.tcena(tp1w[`TP1W_RF_TCENA]),
	.toena(tp1w[`TP1W_RF_TOENA]),
	.tqoena(tp1w[`TP1W_RF_TQOENA]),
	.taa(tp1w[`TP1W_RF_TAA]),
	.clkb(clk),
	.cenb(~we),
	.ab(addrw),
	.db(dataw),
	.tisb(tp1w[`TP1W_RF_TISB]),
	.tmsb(tp1w[`TP1W_RF_TMSB]),
	.tcenb(tp1w[`TP1W_RF_TCENB]),
	.tab(tp1w[`TP1W_RF_TAB]),
	.tdb(tpdw),
	.smsb(tp1w[`TP1W_RF_SMSB]),
	.dsib(tp1w[`TP1W_RF_DSIB])
);
 
// Instantiation of register file memory (B)
art_rf2r_32x32 rf_b(
	.qa(from_rfb),
 
	.oensqa(rfb_tmuxed[`TP1R_RF_OENSQA]),
	.asqa(rfb_tmuxed[`TP1R_RF_ASQA]),
	.tqa(rfb_tqa),
	.qsqa(rfb_tmuxed[`TP1R_RF_QSQA]),
	.dsob(rfb_tmuxed[`TP1R_RF_DSOB]),
	.censqb(rfb_tmuxed[`TP1R_RF_CENSQB]),
	.asqb(rfb_tmuxed[`TP1R_RF_ASQB]),
 
	.clka(clk),
	.cena(1'b0),
	.oena(1'b0),
	.aa(addrb),
	.tisa(tp1w[`TP1W_RF_TISA]),
	.tmsa(tp1w[`TP1W_RF_TMSA]),
	.tcena(tp1w[`TP1W_RF_TCENA]),
	.toena(tp1w[`TP1W_RF_TOENA]),
	.tqoena(tp1w[`TP1W_RF_TQOENA]),
	.taa(tp1w[`TP1W_RF_TAA]),
	.clkb(clk),
	.cenb(~we),
	.ab(addrw),
	.db(dataw),
	.tisb(tp1w[`TP1W_RF_TISB]),
	.tmsb(tp1w[`TP1W_RF_TMSB]),
	.tcenb(tp1w[`TP1W_RF_TCENB]),
	.tab(tp1w[`TP1W_RF_TAB]),
	.tdb(tpdw),
	.smsb(tp1w[`TP1W_RF_SMSB]),
	.dsib(tp1w[`TP1W_RF_DSIB])
);
*/
 
endmodule