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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module sprs(
		// Clk & Rst
		clk, rst,
 
		// Internal CPU interface
		flag, addrbase, addrofs, dat_i, alu_op, branch_op,
		epcr, eear, esr, except_start, except_started,
		to_wbmux, epcr_we, eear_we, esr_we, sr,
 
		// From/to other RISC units
		spr_dat_pic, spr_dat_tt, spr_dat_pm,
		spr_addr, spr_dataout, spr_cs, spr_we
);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O Ports
//
 
//
// Internal CPU interface
//
input				clk; 		// Clock
input 				rst;		// Reset
input 				flag;		// From ALU
input	[width-1:0] 		addrbase;	// SPR base address
input	[15:0] 			addrofs;	// SPR offset
input	[width-1:0]		dat_i;		// SPR write data
input	[`ALUOP_WIDTH-1:0]	alu_op;		// ALU operation
input	[`BRANCHOP_WIDTH-1:0]	branch_op;	// Branch operation
input	[width-1:0] 		epcr;		// EPCR0
input	[width-1:0] 		eear;		// EEAR0
input	[`SR_WIDTH-1:0] 	esr;		// ESR0
input 				except_start;	// Start of exception
input 				except_started; // Exception was started
output	[width-1:0]		to_wbmux;	// For l.mfspr
output				epcr_we;	// EPCR0 write enable
output				eear_we;	// EEAR0 write enable
output				esr_we;		// ESR0 write enable
output	[`SR_WIDTH-1:0]		sr;		// SR
 
//
// To/from other RISC units
//
input	[31:0]			spr_dat_pic;	// Data from PIC
input	[31:0]			spr_dat_tt;	// Data from TT
input	[31:0]			spr_dat_pm;	// Data from PM
output	[31:0]			spr_addr;	// SPR Address
output	[31:0]			spr_dataout;	// Data to unit
output	[31:0]			spr_cs;		// Unit select
output				spr_we;		// SPR write enable
 
//
// Internal regs & wires
//
reg	[`SR_WIDTH-1:0]		sr;		// SR
reg				write_spr;	// Write SPR
reg				read_spr;	// Read SPR
reg	[width-1:0]		to_wbmux;	// For l.mfspr
reg	[31:0]			spr_cs;		// Group selects
wire 				sr_we;		// Write enable SR
wire 				sr_sel;		// Select for SR	
wire 				epcr_sel;	// Select for EPCR0
wire 				eear_sel;	// Select for EEAR0
wire 				esr_sel;	// Select for ESR0
wire	[31:0]			sys_data;	// Read data from system SPRs
wire	[`SR_WIDTH-1:0]		to_sr;		// Data to SR
 
//
// Generate SPR address from base address and offset
//
assign spr_addr = addrbase + addrofs;
 
//
// SPR is written with dat_i
//
assign spr_dataout = dat_i;
 
//
// Write into SPRs when l.mtspr
//
assign spr_we = write_spr;
 
//
// Decoding of groups
//
always @(spr_addr)
	case (spr_addr[`SPR_GROUP_BITS])	// synopsys parallel_case
		`SPR_GROUP_WIDTH'd00: spr_cs <= 32'b00000000_00000000_00000000_00000001;
		`SPR_GROUP_WIDTH'd01: spr_cs <= 32'b00000000_00000000_00000000_00000010;
		`SPR_GROUP_WIDTH'd02: spr_cs <= 32'b00000000_00000000_00000000_00000100;
		`SPR_GROUP_WIDTH'd03: spr_cs <= 32'b00000000_00000000_00000000_00001000;
		`SPR_GROUP_WIDTH'd04: spr_cs <= 32'b00000000_00000000_00000000_00010000;
		`SPR_GROUP_WIDTH'd05: spr_cs <= 32'b00000000_00000000_00000000_00100000;
		`SPR_GROUP_WIDTH'd06: spr_cs <= 32'b00000000_00000000_00000000_01000000;
		`SPR_GROUP_WIDTH'd07: spr_cs <= 32'b00000000_00000000_00000000_10000000;
		`SPR_GROUP_WIDTH'd08: spr_cs <= 32'b00000000_00000000_00000001_00000000;
		`SPR_GROUP_WIDTH'd09: spr_cs <= 32'b00000000_00000000_00000010_00000000;
		`SPR_GROUP_WIDTH'd10: spr_cs <= 32'b00000000_00000000_00000100_00000000;
		`SPR_GROUP_WIDTH'd11: spr_cs <= 32'b00000000_00000000_00001000_00000000;
		`SPR_GROUP_WIDTH'd12: spr_cs <= 32'b00000000_00000000_00010000_00000000;
		`SPR_GROUP_WIDTH'd13: spr_cs <= 32'b00000000_00000000_00100000_00000000;
		`SPR_GROUP_WIDTH'd14: spr_cs <= 32'b00000000_00000000_01000000_00000000;
		`SPR_GROUP_WIDTH'd15: spr_cs <= 32'b00000000_00000000_10000000_00000000;
		`SPR_GROUP_WIDTH'd16: spr_cs <= 32'b00000000_00000001_00000000_00000000;
		`SPR_GROUP_WIDTH'd17: spr_cs <= 32'b00000000_00000010_00000000_00000000;
		`SPR_GROUP_WIDTH'd18: spr_cs <= 32'b00000000_00000100_00000000_00000000;
		`SPR_GROUP_WIDTH'd19: spr_cs <= 32'b00000000_00001000_00000000_00000000;
		`SPR_GROUP_WIDTH'd20: spr_cs <= 32'b00000000_00010000_00000000_00000000;
		`SPR_GROUP_WIDTH'd21: spr_cs <= 32'b00000000_00100000_00000000_00000000;
		`SPR_GROUP_WIDTH'd22: spr_cs <= 32'b00000000_01000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd23: spr_cs <= 32'b00000000_10000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd24: spr_cs <= 32'b00000001_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd25: spr_cs <= 32'b00000010_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd26: spr_cs <= 32'b00000100_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd27: spr_cs <= 32'b00001000_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd28: spr_cs <= 32'b00010000_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd29: spr_cs <= 32'b00100000_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd30: spr_cs <= 32'b01000000_00000000_00000000_00000000;
		`SPR_GROUP_WIDTH'd31: spr_cs <= 32'b10000000_00000000_00000000_00000000;
	endcase
 
//
// SPRs System Group
//
 
//
// What to write into SR
//
assign to_sr = (branch_op == `BRANCHOP_RFE) ? esr : dat_i[`SR_WIDTH-1:0];
 
//
// Selects for system SPRs
//
assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_SR));
assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_EPCR));
assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_EEAR));
assign esr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_ESR));
 
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `BRANCHOP_RFE);
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (sr & {32{read_spr & sr_sel}}) |
		  (epcr & {32{read_spr & epcr_sel}}) |
		  (eear & {32{read_spr & eear_sel}}) |
		  (esr & {32{read_spr & esr_sel}});
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
	if (rst)
		sr <= #1 `SR_WIDTH'b011;
	else if (except_started) begin
		$display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared.");
		sr[`SR_SUPV] <= #1 1'b1;
		sr[`SR_EXR] <= #1 1'b0;
	end
	else if (sr_we) begin
		$display(" INFO: writing into SR register: %h", dat_i);
		sr <= #1 to_sr;
	end
 
//
// MTSPR/MFSPR interface
//
always @(alu_op or spr_addr or dat_i or sys_data or spr_dat_pic or spr_dat_pm or spr_dat_tt) begin
	case (alu_op)	// synopsys full_case parallel_case
		`ALUOP_MTSR : begin
			$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, dat_i);
			write_spr <= #1 1'b1;
			read_spr <= #1 1'b0;
			to_wbmux <= #1 32'b0;
		end
		`ALUOP_MFSR : begin
			casex (spr_addr[`SPR_GROUP_BITS])
				`SPR_GROUP_TT:
					to_wbmux <= #1 spr_dat_tt;
				`SPR_GROUP_PIC:
					to_wbmux <= #1 spr_dat_pic;
				`SPR_GROUP_PM:
					to_wbmux <= #1 spr_dat_pm;
				`SPR_GROUP_SYS:
					to_wbmux <= #1 sys_data;
				default:
					to_wbmux <= #1 32'b0;
			endcase
			write_spr <= #1 1'b0;
			read_spr <= #1 1'b1;
		end
		default : begin
			write_spr <= #1 1'b0;
			read_spr <= #1 1'b0;
			to_wbmux <= #1 32'b0;
		end
	endcase
end
 
endmodule