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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [tt.v] - Rev 209
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's Tick Timer //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// TT according to OR1K architectural specification. //// //// //// //// To Do: //// //// None //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:23 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" module tt( // RISC Internal Interface clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, int ); // // RISC Internal Interface // input clk; // Clock input rst; // Reset input spr_cs; // SPR CS input spr_write; // SPR Write input [31:0] spr_addr; // SPR Address input [31:0] spr_dat_i; // SPR Write Data output [31:0] spr_dat_o; // SPR Read Data output int; // Interrupt output `ifdef TT_IMPLEMENTED // // TT Mode Register bits (or no register) // `ifdef TT_TTMR reg [31:0] ttmr; // TTMR bits `else wire [31:0] ttmr; // No TTMR register `endif // // TT Count Register bits (or no register) // `ifdef TT_TTCR reg [31:0] ttcr; // TTCR bits `else wire [31:0] ttcr; // No TTCR register `endif // // Internal wires & regs // wire ttmr_sel; // TTMR select wire ttcr_sel; // TTCR select wire match; // Asserted when TTMR[TP] // is equal to TTCR[27:0] wire restart; // Restart counter when asserted wire stop; // Stop counter when asserted reg [31:0] spr_dat_o; // SPR data out // // TT registers address decoder // assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0; assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0; // // Write to TTMR or update of TTMR[IP] bit // `ifdef TT_TTMR always @(posedge clk or posedge rst) if (rst) ttmr <= 32'b0; else if (ttmr_sel && spr_write) ttmr <= #1 spr_dat_i; else if (ttmr[`TT_TTMR_IE]) ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int; `else assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3 `endif // // Write to or increment of TTCR // `ifdef TT_TTCR always @(posedge clk or posedge restart) if (restart) ttcr <= 32'b0; else if (ttcr_sel && spr_write) ttcr <= #1 spr_dat_i; else if (!stop) ttcr <= #1 ttcr + 1'd1; `else assign ttcr = 32'b0; `endif // // Read TT registers // always @(spr_addr or ttmr or ttcr) case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case `ifdef TT_READREGS `TT_OFS_TTMR: spr_dat_o = ttmr; `endif default: spr_dat_o = ttcr; endcase // // A match when TTMR[TP] is equal to TTCR[27:0] // assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0; // // Restart when match and TTMR[M]==0x1 or when rst is asserted // assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0; // // Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 // assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0; // // Generate an interrupt request // assign int = match & ttmr[`TT_TTMR_IE]; `else // // When TT is not implemented, drive all outputs as would when TT is disabled // assign int = 1'b0; // // Read TT registers // `ifdef TT_READREGS assign spr_dat_o = 32'b0; `endif `endif endmodule
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