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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's WISHBONE BIU //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Implements WISHBONE interface //// //// //// //// To Do: //// //// - add support for wb_err_i //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // `include "general.h" module wb_biu( // WISHBONE interface wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i, wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o, // Internal RISC bus biu_to_biu, biu_addr, biu_read, biu_write, biu_rdy, biu_from_biu ); parameter dw = `OPERAND_WIDTH; parameter aw = `OPERAND_WIDTH; // // WISHBONE interface // input wb_clk_i; // clock input input wb_rst_i; // reset input input wb_ack_i; // normal termination input wb_err_i; // termination w/ error input wb_rty_i; // termination w/ retry input [dw-1:0] wb_dat_i; // input data bus output wb_cyc_o; // cycle valid output output [aw-1:0] wb_adr_o; // address bus outputs output wb_stb_o; // strobe output output wb_we_o; // indicates write transfer output [3:0] wb_sel_o; // byte select outputs output [dw-1:0] wb_dat_o; // output data bus // // Internal RISC interface // input [dw-1:0] biu_to_biu; // input data bus input [aw-1:0] biu_addr; // address bus input biu_read; // read request input biu_write; // write request output biu_rdy; // data valid output [dw-1:0] biu_from_biu; // output data bus // // WISHBONE I/F <-> Internal RISC I/F conversion // // Address bus assign wb_adr_o = biu_addr; // Input data bus assign biu_from_biu = wb_dat_i; // Output data bus assign wb_dat_o = biu_to_biu; // Acknowledgment of the data to the RISC assign biu_rdy = wb_ack_i; // WB cyc_o assign wb_cyc_o = wb_stb_o; // WB stb_o assign wb_stb_o = biu_read | biu_write; // WB we_o assign wb_we_o = biu_write; // WB sel_o assign wb_sel_o = 4'b1111; endmodule
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