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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [wbmux.v] - Rev 161

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Write-back Mux                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  CPU's write-back stage of the pipeline                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
module wbmux(clk, rst, pipeline_freeze, rfwb_op, muxin_a, muxin_b, muxin_c, muxin_d, muxout, muxreg, muxreg_valid);
 
parameter width = `OPERAND_WIDTH;
 
input clk;
input rst;
input pipeline_freeze;
input [`RFWBOP_WIDTH-1:0] rfwb_op;
input [width-1:0] muxin_a;
input [width-1:0] muxin_b;
input [width-1:0] muxin_c;
input [width-1:0] muxin_d;
 
output [width-1:0] muxout;
output [width-1:0] muxreg;
output muxreg_valid;
 
reg [width-1:0] muxout;
reg [width-1:0] muxreg;
reg muxreg_valid;
 
always @(posedge clk or posedge rst) begin
	if (rst) begin
		muxreg <= #1 32'd0;
		muxreg_valid <= #1 1'b0;
	end
	else if (!pipeline_freeze) begin
		muxreg <= #1 muxout;
		muxreg_valid <= #1 rfwb_op[0];
	end
end
 
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
	case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
		'b00: muxout <= #1 muxin_a;
		'b01: begin
			muxout <= #1 muxin_b;
			$display("  WBMUX: muxin_b %h", muxin_b);
		end
		'b10: begin
			muxout <= #1 muxin_c;
			$display("  WBMUX: muxin_c %h", muxin_c);
		end
		'b11: begin
			muxout <= #1 muxin_d + 4'h8;
			$display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
		end
	endcase
end
 
endmodule
 

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