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/* except.c -- Simulation of OR1K exceptions
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "except.h"
#include "sprs.h"
#include "sim-config.h"
#include "debug_unit.h"
#include "execute.h"
 
extern int cont_run;
extern struct iqueue_entry iqueue[20];
extern unsigned long pc_phy;
extern struct iqueue_entry iqueue[];
 
extern int delay_insn;
 
struct _pending pending;
 
/* Discards all pending exceptions */
void clear_pending_exception()
{
  pending.valid = 0;
  pending.type = 0;
  pending.address = 0;
  pending.saved = 0;
}
 
/* Asserts OR1K exception. */
void except_handle(oraddr_t except, oraddr_t ea)
{
  if(debug_ignore_exception (except)) {
    clear_pending_exception ();
  } else {
    pending.valid = 1;
    pending.type = except;
    pending.address = ea;
    if (delay_insn)
      pending.saved = pc - 4;
    else
      pending.saved = pc;
    if (config.sim.verbose)
      PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR 
             ", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", cycles %lld, #%lld\n",
             except, EXCEPT_NAME(except), iqueue[0].insn_addr, ea, pc, pcnext,
             runtime.sim.cycles, runtime.cpu.instructions);
  }
}
 
/* Actually handles exception */
void except_handle_backend (oraddr_t except, oraddr_t ea, oraddr_t pc_saved)
{
#if ONLY_VIRTUAL_MACHINE
  fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
  cont_run = 0;
#else
 
  if (delay_insn) {
    if (config.sim.verbose) PRINTF("INFO: Exception during execution of delay slot insn.\n");
    pc -= 4;
  }
 
  pc_saved = pc & ~ADDR_C(0x3);
  if (except == EXCEPT_ILLEGAL)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_ALIGN)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_DTLBMISS)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_DPF)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_BUSERR)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_TRAP)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_RANGE)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_ITLBMISS)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else if (except == EXCEPT_IPF)
    mtspr(SPR_EPCR_BASE, pending.saved);
  else
    mtspr(SPR_EPCR_BASE, pc_saved);
 
  mtspr(SPR_EEAR_BASE, ea);
  mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
 
  /* Address translation is always disabled when starting exception. */
  mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
  mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
 
  mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE);	/* Disable overflow flag exception. */
 
  mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM);	/* SUPV mode */
  mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE));	/* Disable interrupts. */
 
  clear_pending_exception ();
 
  pc = (unsigned long)except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
 
  /* This has been removed. All exceptions (not just SYSCALL) suffer
     from the same problem. The solution is to continue just like
     the pipeline would, and issue the exception on the next
     clock cycle. We assume now that this function is being called
     ->BEFORE<- the instruction fetch and after the previous update
     which always yields the correct behavior. This has the added
     advantage that a debugger can prevent an exception from
     taking place by resetting the pc. */
#if 0
  /* MM: We do pc update after the execute (in the simulator), so we
     decrease it by 4 so that next instruction points to first exception
     instruction.  Do NOT comment this out. */
  if (except == EXCEPT_SYSCALL)
    pc -= 4;
#endif
  pcnext = pc + 4;  
 
  /* Added by CZ 27/05/01 */
  pc_phy = pc;      /* An exception always turns off the MMU, so 
           pc is always pc_phy */
 
#endif /* !ONLY_VIRUAL_MACHINE */
}