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/* debug_unit.c -- Simulation of Or1k debug unit Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This is an architectural level simulation of the Or1k debug unit as described in OpenRISC 1000 System Architecture Manual, v. 0.1 on 22 April, 2001. This unit is described in Section 13. Every attempt has been made to be as accurate as possible with respect to the registers and the behavior. There are no known limitations at this time. */ //#define DEBUG_JTAG 0 #include <stdlib.h> #include <stdio.h> #include <string.h> #include "config.h" #ifdef HAVE_INTTYPES_H #include <inttypes.h> #endif #include "port.h" #include "arch.h" #include "debug_unit.h" #include "sim-config.h" #include "except.h" #include "abstract.h" #include "parse.h" #include "sprs.h" #include "gdb.h" #include "except.h" #include "opcode/or32.h" #include "debug.h" DevelopmentInterface development; /* External STALL signal to debug interface */ int in_reset = 0; /* Current watchpoint state */ unsigned long watchpoints = 0; static int calculate_watchpoints(DebugUnitAction action, unsigned long udata); void set_stall_state(int state) { development.riscop &= ~RISCOP_STALL; development.riscop |= state ? RISCOP_STALL : 0; if(testsprbits(SPR_DMR1, SPR_DMR1_DXFW)) /* If debugger disabled */ state = 0; runtime.cpu.stalled = state; } void du_reset() { development.riscop = 0; set_stall_state (0); } void du_clock() { watchpoints=0; }; int CheckDebugUnit(DebugUnitAction action, unsigned long udata) { /* Do not stop, if we have debug module disabled or during reset */ if(!config.debug.enabled || in_reset) return 0; /* If we're single stepping, always stop */ if((action == DebugInstructionFetch) && testsprbits (SPR_DMR1, SPR_DMR1_ST)) return 1; /* is any watchpoint enabled to generate a break or count? If not, ignore */ if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC)) return calculate_watchpoints(action, udata); return 0; } /* Checks whether we should stall the RISC or cause an exception */ static int calculate_watchpoints(DebugUnitAction action, unsigned long udata) { int breakpoint = 0; int i, bit; /* Hopefully this loop would be unrolled run at max. speed */ for(i = 0, bit = 1; i < 11; i++, bit <<= 1) { int chain1, chain2; int match = 0; int DCR_hit = 0; /* Calculate first 8 matchpoints, result is put into DCR_hit */ if (i < 8) { unsigned long dcr = mfspr(SPR_DCR(i)); unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */ /* Is this matchpoint a propos for the current action? */ if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */ (((action==DebugInstructionFetch) && (dcr_ct == SPR_DCR_CT_IFEA)) || ((action==DebugLoadAddress) && ((dcr_ct == SPR_DCR_CT_LEA) || (dcr_ct == SPR_DCR_CT_LSEA))) || ((action==DebugStoreAddress) && ((dcr_ct == SPR_DCR_CT_SEA) || (dcr_ct == SPR_DCR_CT_LSEA))) || ((action==DebugLoadData) && ((dcr_ct == SPR_DCR_CT_LD) || (dcr_ct == SPR_DCR_CT_LSD))) || ((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) || (dcr_ct == SPR_DCR_CT_LSD)))) ) { unsigned long op1 = udata; unsigned long op2 = mfspr (SPR_DVR(i)); /* Perform signed comparison? */ if (dcr & SPR_DCR_SC) { long sop1 = op1, sop2 = op2; /* Convert to signed */ switch(dcr & SPR_DCR_CC) { case SPR_DCR_CC_MASKED: DCR_hit = sop1 & sop2; break; case SPR_DCR_CC_EQUAL: DCR_hit = sop1 == sop2; break; case SPR_DCR_CC_NEQUAL: DCR_hit = sop1 != sop2; break; case SPR_DCR_CC_LESS: DCR_hit = sop1 < sop2; break; case SPR_DCR_CC_LESSE: DCR_hit = sop1 <= sop2; break; case SPR_DCR_CC_GREAT: DCR_hit = sop1 > sop2; break; case SPR_DCR_CC_GREATE: DCR_hit = sop1 >= sop2; break; } } else { switch(dcr & SPR_DCR_CC) { case SPR_DCR_CC_MASKED: DCR_hit = op1 & op2; break; case SPR_DCR_CC_EQUAL: DCR_hit = op1 == op2; break; case SPR_DCR_CC_NEQUAL: DCR_hit = op1 != op2; break; case SPR_DCR_CC_LESS: DCR_hit = op1 < op2; break; case SPR_DCR_CC_LESSE: DCR_hit = op1 <= op2; break; case SPR_DCR_CC_GREAT: DCR_hit = op1 > op2; break; case SPR_DCR_CC_GREATE: DCR_hit = op1 >= op2; break; } } } } /* Chain matchpoints */ switch(i) { case 0: chain1 = chain2 = DCR_hit; break; case 8: chain1 = getsprbits(SPR_DWCR0, SPR_DWCR_COUNT) == getsprbits(SPR_DWCR0, SPR_DWCR_MATCH); chain2 = watchpoints & (1 << 7); break; case 9: chain1 = getsprbits(SPR_DWCR1, SPR_DWCR_COUNT) == getsprbits (SPR_DWCR1, SPR_DWCR_MATCH); chain2 = watchpoints & (1 << 8); break; case 10: /* TODO: External watchpoint - not yet handled! */ #if 0 chain1 = external_watchpoint; chain2 = watchpoints & (1 << 9); #else chain1 = chain2 = 0; #endif break; default: chain1 = DCR_hit; chain2 = watchpoints & (bit >> 1); break; } switch(getsprbits(SPR_DMR1, SPR_DMR1_CW0 << i)) { case 0: match = chain1; break; case 1: match = chain1 && chain2; break; case 2: match = chain1 || chain2; break; } /* Increment counters & generate counter break */ if(match) { /* watchpoint did not appear before in this clock cycle */ if(!(watchpoints & bit)) { int counter = (getsprbits(SPR_DMR2, SPR_DMR2_AWTC) & bit) ? 1 : 0; int enabled = counter ? getsprbits(SPR_DMR2, SPR_DMR2_WCE1) : getsprbits(SPR_DMR2, SPR_DMR2_WCE0); if(enabled) setsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT, getsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT) + 1); watchpoints |= bit; } /* should this watchpoint generate a breakpoint? */ if(getsprbits(SPR_DMR2, SPR_DMR2_WGB) & bit) breakpoint = 1; } } return breakpoint; } static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL; int DebugGetRegister(unsigned int address, unsigned long* data) { int err=0; #ifdef DEBUG_JTAG PRINTF("Debug get register %x\n",address); fflush(stdout); #endif switch(current_scan_chain) { case JTAG_CHAIN_DEBUG_UNIT: *data = mfspr (address); debug (2, "READ (%08x) = %08x\n", address, *data); if (runtime.sim.fspr_log) { fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n", address, *data); } break; case JTAG_CHAIN_TRACE: *data = 0; /* Scan chain not yet implemented */ break; case JTAG_CHAIN_DEVELOPMENT: err = get_devint_reg(address,data); break; case JTAG_CHAIN_WISHBONE: err = debug_get_mem(address,data); break; } #ifdef DEBUG_JTAG PRINTF("!get reg %x\n", *data); fflush(stdout); #endif return err; } int DebugSetRegister(unsigned int address,unsigned long data) { int err=0; #ifdef DEBUG_JTAG PRINTF("Debug set register %x <- %x\n", address, data); fflush(stdout); #endif switch(current_scan_chain) { case JTAG_CHAIN_DEBUG_UNIT: debug (2, "WRITE (%08x) = %08lx\n", address, data); if (runtime.sim.fspr_log) { fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n", address, data); } mtspr(address, data); break; case JTAG_CHAIN_TRACE: err = JTAG_PROXY_ACCESS_EXCEPTION; break; case JTAG_CHAIN_DEVELOPMENT: err = set_devint_reg (address, data); break; case JTAG_CHAIN_WISHBONE: err = debug_set_mem (address, data); break; } #ifdef DEBUG_JTAG PRINTF("!set reg\n"); fflush(stdout); #endif return err; } int DebugSetChain(int chain) { #ifdef DEBUG_JTAG PRINTF("Debug set chain %x\n",chain); fflush(stdout); #endif switch(chain) { case JTAG_CHAIN_DEBUG_UNIT: case JTAG_CHAIN_TRACE: case JTAG_CHAIN_DEVELOPMENT: case JTAG_CHAIN_WISHBONE: current_scan_chain = chain; break; default: /* All other chains not implemented */ return JTAG_PROXY_INVALID_CHAIN; } #ifdef DEBUG_JTAG PRINTF("!set chain\n"); fflush(stdout); #endif return 0; } void sim_reset (); /* Sets development interface register */ int set_devint_reg(unsigned int address, unsigned long data) { int err = 0; unsigned long value = data; int old_value; switch(address) { case DEVELOPINT_MODER: development.moder = value; break; case DEVELOPINT_TSEL: development.tsel = value; break; case DEVELOPINT_QSEL: development.qsel = value; break; case DEVELOPINT_SSEL: development.ssel = value; break; case DEVELOPINT_RISCOP: old_value = (development.riscop & RISCOP_RESET) != 0; development.riscop = value; in_reset = (development.riscop & RISCOP_RESET) != 0; /* Reset the cpu on the negative edge of RESET */ if(old_value && !in_reset) sim_reset(); /* Reset all units */ set_stall_state((development.riscop & RISCOP_STALL) != 0); break; case DEVELOPINT_RECWP0: case DEVELOPINT_RECWP1: case DEVELOPINT_RECWP2: case DEVELOPINT_RECWP3: case DEVELOPINT_RECWP4: case DEVELOPINT_RECWP5: case DEVELOPINT_RECWP6: case DEVELOPINT_RECWP7: case DEVELOPINT_RECWP8: case DEVELOPINT_RECWP9: case DEVELOPINT_RECWP10: development.recwp[address - DEVELOPINT_RECWP0] = value; break; case DEVELOPINT_RECBP0: development.recbp = value; break; default: err = JTAG_PROXY_INVALID_ADDRESS; break; } #ifdef DEBUG_JTAG PRINTF("set_devint_reg %08x = %08x\n", address, data); fflush(stdout); #endif return err; } /* Gets development interface register */ int get_devint_reg(unsigned int address,unsigned long *data) { int err = 0; unsigned long value = 0; switch(address) { case DEVELOPINT_MODER: value = development.moder; break; case DEVELOPINT_TSEL: value = development.tsel; break; case DEVELOPINT_QSEL: value = development.qsel; break; case DEVELOPINT_SSEL: value = development.ssel; break; case DEVELOPINT_RISCOP: value = development.riscop; break; case DEVELOPINT_RECWP0: case DEVELOPINT_RECWP1: case DEVELOPINT_RECWP2: case DEVELOPINT_RECWP3: case DEVELOPINT_RECWP4: case DEVELOPINT_RECWP5: case DEVELOPINT_RECWP6: case DEVELOPINT_RECWP7: case DEVELOPINT_RECWP8: case DEVELOPINT_RECWP9: case DEVELOPINT_RECWP10: value = development.recwp[address - DEVELOPINT_RECWP0]; break; case DEVELOPINT_RECBP0: value = development.recbp; break; default: err = JTAG_PROXY_INVALID_ADDRESS; break; } #ifdef DEBUG_JTAG PRINTF("get_devint_reg %08x = %08x\n", address, value); fflush(stdout); #endif *data = value; return err; } /* Writes to bus address */ int debug_set_mem (unsigned int address,unsigned long data) { int err = 0; debug (2, "MEMWRITE (%08x) = %08lx\n", address, data); if(!verify_memoryarea(address)) err = JTAG_PROXY_INVALID_ADDRESS; else { // circumvent the read-only check usually done for mem accesses // data is in host order, because that's what simmem_write_word needs simmem_write_word(address, data); } return err; } /* Reads from bus address */ int debug_get_mem(unsigned int address,unsigned long *data) { int err = 0; if(!verify_memoryarea(address)) err = JTAG_PROXY_INVALID_ADDRESS; else { *data=simmem_read_word(address); } debug (2, "MEMREAD (%08x) = %08lx\n", address, *data); return err; } /* debug_ignore_exception returns 1 if the exception should be ignored. */ int debug_ignore_exception (unsigned long except) { int result = 0; unsigned long dsr = mfspr (SPR_DSR); unsigned long drr = mfspr (SPR_DRR); #if DEBUG_JTAG PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr); #endif switch(except) { case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break; case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break; case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break; case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break; case EXCEPT_TICK: drr |= result = dsr & SPR_DSR_TTE; break; case EXCEPT_ALIGN: drr |= result = dsr & SPR_DSR_AE; break; case EXCEPT_ILLEGAL: drr |= result = dsr & SPR_DSR_IIE; break; case EXCEPT_INT: drr |= result = dsr & SPR_DSR_IE; break; case EXCEPT_DTLBMISS: drr |= result = dsr & SPR_DSR_DME; break; case EXCEPT_ITLBMISS: drr |= result = dsr & SPR_DSR_IME; break; case EXCEPT_RANGE: drr |= result = dsr & SPR_DSR_RE; break; case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break; case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break; default: break; } #if DEBUG_JTAG PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result); #endif mtspr (SPR_DRR, drr); set_stall_state (result != 0); return (result != 0); }
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