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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
#include "vapi.h"
#include "sched.h"
#include "channel.h"
#include "debug.h"
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
 
static struct dev_16450 uarts[MAX_UARTS];			/* simulation info */
static struct channel * channels[MAX_UARTS] = { NULL, };	/* emulation info */
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
  float bauds_per_char = 1.;
  unsigned long char_clks = ((dlh << 8) + dll);
 
  if (lcr & UART_LCR_PARITY)
    bauds_per_char = bauds_per_char + 1.;
 
  /* stop bits 1 or two */
  if (lcr & UART_LCR_STOP)
    bauds_per_char = bauds_per_char + 2.;
  else
    if ((lcr & 0x3) != 0)
      bauds_per_char = bauds_per_char + 1.;
    else 
      bauds_per_char = bauds_per_char + 1.5;
 
  bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));
 
  return char_clks * bauds_per_char;
}
 
/* Set a specific UART register with value. */
void uart_write_byte(oraddr_t addr, uint32_t value)
{
  int chipsel;
 
  debug(4, "uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);
 
  for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
    if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
      break;
  if (chipsel >= MAX_UARTS) return;
 
  if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        uarts[chipsel].regs.dll = value;
        uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
        return;
      case UART_DLH:
        uarts[chipsel].regs.dlh = value;
        return;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_TXBUF:
      if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
        uarts[chipsel].istat.txbuf_full++;        
        uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
        uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;
      } else
        uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;
 
      uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
      if (uarts[chipsel].regs.iir & UART_IIR_THRI)
	uarts[chipsel].istat.thre_int = 0;
      break;
    case UART_FCR:
      uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
      if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
       || uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))
        value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
      uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
      if (value & UART_FCR_RTXFI) {
        uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
        uarts[chipsel].istat.txbuf_full = 0;
        uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
 
	// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
	uarts[chipsel].istat.thre_int = (uarts[chipsel].fifo_len == 16);
      }
      if (value & UART_FCR_RRXFI) {
        uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
        uarts[chipsel].istat.rxbuf_full = 0;
        uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
      }
      break;
    case UART_IER:
      uarts[chipsel].regs.ier = value & UART_VALID_IER;
      break;
    case UART_LCR:
      uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
      uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
      break;
    case UART_MCR:
      uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
      break;
    case UART_SCR:
      uarts[chipsel].regs.scr = value;
      break;
    default:
      debug(1, "write out of range (addr %x)\n", addr);
  }
}
 
/* Read a specific UART register. */
uint32_t uart_read_byte(oraddr_t addr)
{
  uint8_t value = 0;
  int chipsel;
 
  debug(4, "uart_read_byte(%"PRIxADDR")", addr);
 
  for(chipsel = 0; chipsel < MAX_UARTS; chipsel++)
    if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
      break;
 
  if (chipsel >= MAX_UARTS)
    return 0;
 
  if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        value = uarts[chipsel].regs.dll;
        debug(4, "= %"PRIx8"\n", value);
        return value;
      case UART_DLH:
        value = uarts[chipsel].regs.dlh;
        debug(4, "= %"PRIx8"\n", value);
        return value;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_RXBUF:
      { /* Print out FIFO for debugging */
        int i;
        debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,
                  uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);
        for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)
          debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);
        debug(4, ")");
      }
      if (uarts[chipsel].istat.rxbuf_full) {
        value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
        uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
        uarts[chipsel].istat.rxbuf_full--;
      }
 
      if (uarts[chipsel].istat.rxbuf_full)
        uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
      else
        uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
 
      uarts[chipsel].istat.timeout_count = 0;
      break;
    case UART_IER:
      value = uarts[chipsel].regs.ier & UART_VALID_IER;
      break;
    case UART_IIR:
      value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
      if (uarts[chipsel].regs.iir & UART_IIR_THRI)
        uarts[chipsel].istat.thre_int = 0;
      break;
    case UART_LCR:
      value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
      break;
    case UART_MCR:
      value = 0;
      break;
    case UART_LSR:
      value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
      uarts[chipsel].regs.lsr &=
        ~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
         | UART_LSR_FRAME | UART_LSR_RXERR);
      break;
    case UART_MSR:
      value = uarts[chipsel].regs.msr & UART_VALID_MSR;
      uarts[chipsel].regs.msr = 0;
      break;
    case UART_SCR:
      value = uarts[chipsel].regs.scr;
      break;
    default:
      debug(1, "read out of range (addr %"PRIxADDR")\n", addr);
  }
  debug(4, " = %"PRIx8"\n", value);
  return value;
}
 
/* Function that handles incoming VAPI data.  */
void uart_vapi_read (unsigned long id, unsigned long data)
{
  int uart;
  debug(4, "UART: id %08lx, data %08lx\n", id, data);
  uart = id & VAPI_DEVICE_ID;
  uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
  uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
  if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
    fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
    exit (1);
  }
}
 
static void send_char (int uart, int bits_send)
{
  PRINTF ("%c", (char)uarts[uart].iregs.txser);
  debug(4, "TX \'%c\' via UART%d...\n", (char)uarts[uart].iregs.txser, uart);
  if (uarts[uart].regs.mcr & UART_MCR_LOOP)
    uarts[uart].iregs.loopback = uarts[uart].iregs.txser;
  else {
    /* Send to either VAPI or to file */
    if (config.uarts[uart].vapi_id) {
      int par, pe, fe, nbits;
      int j, data;
      unsigned long packet = 0;
 
      nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);
      /* Encode a packet */
      packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);
 
      /* Calculate parity */
      for (j = 0, par = 0; j < nbits; j++)
        par ^= (packet >> j) & 1;
 
      if (uarts[uart].regs.lcr & UART_LCR_PARITY) {
        if (uarts[uart].regs.lcr & UART_LCR_SPAR) {
          packet |= 1 << nbits;
        } else {
          if (uarts[uart].regs.lcr & UART_LCR_EPAR)
            packet |= par << nbits;
          else
            packet |= (par ^ 1) << nbits;
        }
        nbits++;
      }
      packet |= 1 << (nbits++);
      if (uarts[uart].regs.lcr & UART_LCR_STOP)
        packet |= 1 << (nbits++);
 
      /* Decode a packet */
      nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;
      data = packet & ((1 << nbits) - 1);
 
      /* Calculate parity, including parity bit */
      for (j = 0, par = 0; j < nbits + 1; j++)
        par ^= (packet >> j) & 1;
 
      if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {
        if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {
          pe = !((packet >> nbits) & 1);
        } else {
          if (uarts[uart].vapi.lcr & UART_LCR_EPAR)
            pe = par != 0;
          else
            pe = par != 1;
        }
        nbits++;
      } else
        pe = 0;
 
      fe = ((packet >> (nbits++)) & 1) ^ 1;
      if (uarts[uart].vapi.lcr & UART_LCR_STOP)
        fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
      debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);
      data |= (uarts[uart].vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uarts[uart].vapi.lcr << 8);
      PRINTF ("vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);
      debug (4, "vapi_send (%08lx, %08x)\n", config.uarts[uart].vapi_id, data);
      vapi_send (config.uarts[uart].vapi_id, data);
    } else {
      char buffer[1] = { uarts[uart].iregs.txser & 0xFF };
      channel_write(channels[uart], buffer, 1);
    }
  }
  uarts[uart].istat.txser_full = 0;
  uarts[uart].istat.txser_clks = 0;
}
 
/* Adds a character to the FIFO */
 
void uart_add_char (int uart, int ch)
{
  if (uarts[uart].istat.rxbuf_full + 1 > uarts[uart].fifo_len)
    uarts[uart].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
  else {
    debug(4, "add %02x\n", ch);
    uarts[uart].regs.rxbuf[uarts[uart].istat.rxbuf_head] = ch;
    uarts[uart].istat.rxbuf_head = (uarts[uart].istat.rxbuf_head + 1) % uarts[uart].fifo_len;
    uarts[uart].istat.rxbuf_full++;
  }
  uarts[uart].regs.lsr |= UART_LSR_RDRDY;
  uarts[uart].istat.timeout_count = 0;
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock16 (int i)
{
  int retval;
 
  /* Schedule for later */
  SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
 
  /* If VAPI is not selected, UART communicates with two file streams;
     if VAPI is selected, we use VAPI streams.  */
  /* if txfs is corrupted, skip this uart. */
  if (!config.uarts[i].vapi_id && !channel_ok(channels[i])) return;
 
  if (uarts[i].vapi.next_break_cnt >= 0)
    if (--uarts[i].vapi.next_break_cnt < 0) {
      if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
        uarts[i].istat.break_set = 0;
    }
 
  /***************** Transmit *****************/
  if (!uarts[i].istat.txser_full) {
//      uarts[i].regs.lsr |= UART_LSR_TXBUFE;
    if (uarts[i].istat.txbuf_full) {
      uarts[i].iregs.txser = uarts[i].regs.txbuf[uarts[i].istat.txbuf_tail];
      uarts[i].istat.txbuf_tail = (uarts[i].istat.txbuf_tail + 1) % uarts[i].fifo_len;
      uarts[i].istat.txser_full = 1;
      uarts[i].istat.txbuf_full--;
      uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
 
      // When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
      // the THRE interrupt is raised when THR transitions from full to empty.
      if (!uarts[i].istat.txbuf_full) {
	uarts[i].istat.thre_int = 1;
	uarts[i].regs.lsr |= UART_LSR_TXBUFE;
      }
    } else {
      uarts[i].regs.lsr |= UART_LSR_TXSERE;
    }
  } else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
    send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
  } else {
    /* We are still sending char here*/
 
    /* Check if we set the break bit */
    if (uarts[i].regs.lcr & UART_LCR_SBC) {
      if (!uarts[i].vapi.break_sent) {
#if 0
        /* Send broken frame */
        int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;
        send_char(i, nbits_sent);
#endif
        /* Send one break signal */
        vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);
        uarts[i].vapi.break_sent = 1;
      }
      /* mark as character was sent */
      uarts[i].istat.txser_full = 0;
      uarts[i].istat.txser_clks = 0;
    } else
      uarts[i].vapi.break_sent = 0;
 
  }
 
  /***************** Receive *****************/
 
  /* Is there a break? */
  if (uarts[i].vapi.cur_break) {
    uarts[i].vapi.cur_break_cnt++;
    if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
      if (!uarts[i].istat.break_set) {
        unsigned lsr;
        uarts[i].istat.break_set = 1;
        lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
        PRINTF ("[%x]\n", uarts[i].regs.lsr);
        uarts[i].istat.rxser_full = 0;
        uarts[i].istat.rxser_clks = 0;
        uart_add_char (i, lsr << 8);
      } else
        uarts[i].vapi.cur_break_cnt = 0;
    }
    if (uarts[i].istat.rxser_full) {
      uarts[i].istat.rxser_full = 0;
      uarts[i].istat.rxser_clks = 0;
    }
  } else {
    if (uarts[i].istat.rxser_full) {
      if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
        /* Set unused character bits to zero and allow lsr register in fifo */
        uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1) | 0xff00;
        debug(4, "Receiving 0x%02lx'%c' via UART%d...\n", uarts[i].iregs.rxser,
              (char)uarts[i].iregs.rxser, i);
	PRINTF ("%c", (char)uarts[i].iregs.rxser);
        uarts[i].istat.rxser_full = 0;
        uarts[i].istat.rxser_clks = 0;
        uart_add_char (i, uarts[i].iregs.rxser);
      }
    }
  }
 
  /* Check if there is something waiting, and put it into rxser */
  if (uarts[i].regs.mcr & UART_MCR_LOOP) {
    uarts[i].iregs.rxser = uarts[i].iregs.loopback;
    uarts[i].istat.rxser_full = 1;
  } else {
    if (!config.uarts[i].vapi_id) {
      if(uarts[i].istat.rxser_full == 0) {
        if (uarts[i].slowdown)
          uarts[i].slowdown--;
        else {
	  char buffer[1];
	  retval = channel_read(channels[i], buffer, 1);
	  if(retval < 0)
		  perror(config.uarts[i].channel);
	  else if(retval > 0) {
            uarts[i].iregs.rxser = (unsigned char)buffer[0];
            uarts[i].istat.rxser_full = 1;
	  } else
            uarts[i].slowdown = UART_FGETC_SLOWDOWN;
	}
      }
    } else { /* VAPI */
      int received = 0;
      /* do not handle commands while receiving */
      if (uarts[i].istat.rxser_full) return;
      while (!received) {
        if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
          unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
          debug(4, "Handling: %08lx (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
          uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
          switch (data >> 24) {
            case 0x00:
              uarts[i].vapi.lcr = (data >> 8) & 0xff;
              /* Put data into rx fifo */
              uarts[i].iregs.rxser = data & 0xff;
              uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
              if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
               || uarts[i].vapi.char_clks != uarts[i].char_clks
               || uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
                debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
                      uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
                /* Set error bits */
                uarts[i].iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
                if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].iregs.rxser |= UART_LSR_PARITY << 8;
              }
              uarts[i].istat.rxser_full = 1;
              received = 1;
              break;
            case 0x01:
              uarts[i].vapi.dll = (data >> 0) & 0xff;
              uarts[i].vapi.dlh = (data >> 8) & 0xff;
              break;
            case 0x02:
              uarts[i].vapi.lcr = (data >> 8) & 0xff;
              break;
            case 0x03:
              uarts[i].vapi.skew = (signed short)(data & 0xffff);
              break;
            case 0x04:
              uarts[i].vapi.next_break_cnt = data & 0xffff;
              uarts[i].vapi.next_break = (data >> 16) & 1;
              break;
            default:
              debug (0, "WARNING: Invalid vapi command %02lx\n", data >> 24);
              break;
          }
        } else break;
      }
    }
  }
 
  /***************** Loopback *****************/
  if (uarts[i].regs.mcr & UART_MCR_LOOP) {
    debug(5, "uart_clock: Loopback\n");
    if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
        ((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
      uarts[i].regs.msr |= UART_MSR_DDCD;
    if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
        ((uarts[i].regs.msr & UART_MSR_RI) >> 4))
      uarts[i].regs.msr |= UART_MSR_TERI;
    if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
        ((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
      uarts[i].regs.msr |= UART_MSR_DCTS;
    if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
        ((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
      uarts[i].regs.msr |= UART_MSR_DDSR;
    uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
              | UART_MSR_DSR | UART_MSR_CTS);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
    uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
  }
 
  if (uarts[i].regs.lsr & UART_LSR_RDRDY)
    uarts[i].istat.timeout_count++;
 
  /* Update LSR error bits from the ones from rx FIFO */
  if (uarts[i].istat.rxbuf_full) {
    uarts[i].regs.lsr |= uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] >> 8;
    /* we must delete the lsr status, so that we can clear it from lsr */
    uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_tail] &= 0xff;
  }
 
  /* Interrupt detection in proper priority order. */
  uarts[i].regs.iir = UART_IIR_NO_INT;
  if (uarts[i].regs.ier & UART_IER_RLSI &&                    /* Receiver LS */
      uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
        | UART_LSR_FRAME | UART_LSR_BREAK)) {
    uarts[i].regs.iir = UART_IIR_RLSI;
  } else if ((uarts[i].regs.ier & UART_IER_RDI)               /* RD available */
      && (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
      && (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
    uarts[i].regs.iir = UART_IIR_RDI;
  } else if ((uarts[i].regs.ier & UART_IER_RDI)               /* timeout */
      && (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)
      && (uarts[i].istat.rxbuf_head != uarts[i].istat.rxbuf_tail)) {
    uarts[i].regs.iir = UART_IIR_CTI;
  } else if (uarts[i].regs.ier & UART_IER_THRI &&             /* Transm. empty */
      uarts[i].istat.thre_int == 1) {
    uarts[i].regs.iir = UART_IIR_THRI;
  } else if (uarts[i].regs.ier & UART_IER_MSI &&              /* Modem status */
      uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
        | UART_MSR_TERI | UART_MSR_DDCD)) {
    uarts[i].regs.iir = UART_IIR_MSI;
  }
  if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
    debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
    report_interrupt(config.uarts[i].irq);
  }
}
 
/* Reset.  It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space.  */
void uart_reset()
{
  int i;
  if (config.sim.verbose && config.nuarts) PRINTF("Resetting %u UART(s).\n", config.nuarts);
  memset(uarts, 0, sizeof(uarts));
 
  for(i = 0; i < config.nuarts; i++) {
    if (config.uarts[i].vapi_id) {
      if ((config.uarts[i].vapi_id & VAPI_DEVICE_ID) != i) {
        fprintf (stderr, "ERROR: Wrong vapi_id (0x%lx) for uart %i, last byte is required to be %02x; ignoring.\n", config.uarts[i].vapi_id, i, i);
        config.uarts[i].vapi_id = 0;
      } else {
        vapi_install_handler (config.uarts[i].vapi_id, uart_vapi_read);
        register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
      }
    } else if (config.uarts[i].channel[0]) { /* MM: Try to create stream.  */
      if(channels[i])
        channel_close(channels[i]);
      else
        channels[i] = channel_init(config.uarts[i].channel);
      if(channel_open(channels[i]) < 0) {
        debug (0, "WARNING: UART%d has problems with channel \"%s\".\n", i, config.uarts[i].channel);
        continue;
      }
      if (config.sim.verbose)
        PRINTF("UART%d at 0x%.8lx uses ", i, config.uarts[i].baseaddr);
      register_memoryarea(config.uarts[i].baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte, uart_write_byte);
    } else {
        debug (0, "WARNING: UART%d has no vapi nor channel specified\n", i);
	continue;
    }
 
    if (config.uarts[i].uart16550)
      uarts[i].fifo_len = 16;
    else
      uarts[i].fifo_len = 1;
 
    uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
    uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
 
    uarts[i].istat.break_set = 0;
    uarts[i].istat.timeout_count = 0;
 
    // For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
    uarts[i].istat.thre_int = (uarts[i].fifo_len == 16);
 
    uarts[i].slowdown = UART_FGETC_SLOWDOWN;
 
    uarts[i].regs.lcr = UART_LCR_RESET;
    uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
    uarts[i].vapi.next_break_cnt = -1;
    PRINTF ("%i\n", i);
    SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
  }
}
 
/* Print register values on stdout. */
void uart_status()
{
  int i, j;
 
  for(i = 0; i < config.nuarts; i++) {
    if ( !config.uarts[i].baseaddr )
      continue;
    PRINTF("\nUART%d visible registers at 0x%.8lx:\n", i,
           config.uarts[i].baseaddr);
    PRINTF("RXBUF: ");
    for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
      PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
    PRINTF("TXBUF: ");
    for (j = uarts[i].istat.txbuf_head; j != uarts[i].istat.txbuf_tail; j = (j + 1) % uarts[i].fifo_len)
      PRINTF (" %.2x", uarts[i].regs.txbuf[j]);
    PRINTF("\n");
    PRINTF("DLL  : %.2x  DLH  : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
    PRINTF("IER  : %.2x  IIR  : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
    PRINTF("LCR  : %.2x  MCR  : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
    PRINTF("LSR  : %.2x  MSR  : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
    PRINTF("SCR  : %.2x\n", uarts[i].regs.scr);
 
    PRINTF("\nInternal registers (sim debug):\n");
    PRINTF("RXSER: %.2lx  TXSER: %.2lx\n", uarts[i].iregs.rxser,
           uarts[i].iregs.txser);
 
    PRINTF("\nInternal status (sim debug):\n");
    PRINTF("char_clks: %ld\n", uarts[i].char_clks);
    PRINTF("rxser_clks: %ld  txser_clks: %ld\n", uarts[i].istat.rxser_clks,
           uarts[i].istat.txser_clks);
    PRINTF("rxser: %d  txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
    PRINTF("rxbuf_full: %d  txbuf_full: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
    PRINTF("Using IRQ%i\n", config.uarts[i].irq);
    if (config.uarts[i].vapi_id)
      PRINTF ("Connected to vapi ID=%lx\n\n", config.uarts[i].vapi_id);
    /* TODO: replace by a channel_status
    else
      PRINTF("RX fs: %p  TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
    */
  }
}