OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [acv_uart.cfg] - Rev 478

Go to most recent revision | Compare with Previous | Blame | View Log

section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
  
  nmemories = 2
  device 0
    name = "RAM"
    ce = 0
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
  
  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 2
    delayw = 4
  enddevice
end

section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
  slp = 0
  btic = 0
  bpb = 0
end

section sim
  debug = 4 
  profile = 0
  prof_fn = "sim.profile"
  
  verbose = 1
  /* iprompt = 0 */
  exe_log = 1
  exe_log_fn = "executed.log"
end

section uart
  enabled = 1
  nuarts = 1
  
  device 0
    baseaddr = 0x9c000000
    jitter = -1                     /* async behaviour */
    16550 =  1
    irq = 15
    vapi_id = 0x100
  enddevice
end

section VAPI
  enabled = 1
  log_enabled = 1
  hide_device_id = 1
  vapi_log_fn = "vapi.log"
  server_port = 9100
end

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.