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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [tick/] [tick.c] - Rev 91
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/* tick.c -- Simulation of OpenRISC 1000 tick timer Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This is functional simulation of OpenRISC 1000 architectural tick timer. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include "tick.h" #include "../cpu/or1k/spr_defs.h" static unsigned long timer; /* Reset. It initializes TTCR register. */ void tick_reset() { printf("Resetting Tick Timer.\n"); mtspr(SPR_TTCR, 0); } /* Simulation hook. Must be called every clock cycle to simulate tick timer. It does internal functional tick timer simulation. */ void tick_clock() { unsigned long ttcr; ttcr = mfspr(SPR_TTCR); if (!(ttcr & SPR_TTCR_TTE)) return; if (timer == 0) { if (!(ttcr & SPR_TTCR_SR)) timer = ttcr & SPR_TTCR_PERIOD; if (ttcr & SPR_TTCR_IE) { setsprbits(SPR_TTCR, SPR_TTCR_IP, 1); report_interrupt(); } } if (timer) timer--; }
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