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What is this stuff?
===================

This is OpenRISC 1000 and DLX architectural simulator. It was written by
Damjan Lampret and it is free software. See the file COPYING for copying
permission. To contact the author, send mail to <lampret@opencores.org>.

I use it to define OR1K system architecture. An implementation simulator
for OR1K will be also available, probably in Nov/1999.

Initially this software was not meant to be released to public because it
was developed just to analyze program flow of GCC generated assembly code.
With the time it became bigger and was able to generate statistics about
superscalar issuing of multiple instructions. I've used it as a test simulator
to test OR1K GCC port. Perhaps some day I will (or perhaps someone else would
like to do that ??) clean-up the code and reorganize it.

This simulator loads an assembly file for one of the both architectures
and it simulates the operation of instructions. Because it was meant to be used
only to test characteristics of various RISC architectures and various GCC
optimization methods, it has a bit strange memory model. It is abstract and
physical at the same time. I can't really explain, just check the sources if
interested. Some other things are strange or incomplete too (like
C library emulation, currently supports only printf).

cache and mmu directories are still empty. Someday (Nov/1999 probably) they
will be filled with code for cache simulation and with code for virtual
memory simulation.


Installation
============

To compile just issue "make all" command. By default there should be no
warnings. There is no "make install". Just use it from default location
or copy it to your bin directory (usually something like /usr/local/bin
or ~/bin).
This program hasn't been written with security in mind. It has many static
buffers and it does not check the size of input strings (user commands
or whatever). So don't setuid it. If it kills your dog, don't blame it on me.

To select DLX simulation, change CPU_ARCH in top level Makefile to 'dlx'
and recompile everything (do 'make all' again).

Simulator test
==============

Issue 'or1ksim testbench/dhry.or1k' or 'dlxsim testbench/dhry.dlx' to
test simulator. Use 'help' to get list of simulator commands.
Run simulation with 'run 1000000 hush'. It will take
a couple of seconds and you should get an error about label _exit.
Now quit simulator with 'q' and open file stdout.txt. You should see
output from simulated dhrystone benchmark.
See testbench/README for details about Dhrystone 2.1 benchmark.

OpenRISC and open cores
=======================

About the same idea as with GNU project except we want free hardware
IP (intellectual property). We design open source, synthesizeable
cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
will run GNU/Linux.
For more information visit us at http://www.opencores.org.

--

24/Oct/1999, Damjan Lampret email:lampret@opencores.org