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/* mc_async.c - Memory Controller testbench ASYNCdevice test
	 Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
 
	 This file is part of OpenRISC 1000 Architectural Simulator.
 
	 This program is free software; you can redistribute it and/or modify
	 it under the terms of the GNU General Public License as published by
	 the Free Software Foundation; either version 2 of the License, or
	 (at your option) any later version.
 
	 This program is distributed in the hope that it will be useful,
	 but WITHOUT ANY WARRANTY; without even the implied warranty of
	 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
	 GNU General Public License for more details.
 
	 You should have received a copy of the GNU General Public License
	 along with this program; if not, write to the Free Software
	 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
#include "support.h"
 
#include "mc_common.h"
#include "mc_async.h"
#include "../peripheral/mc.h"
#include "../peripheral/fields.h"
 
typedef volatile unsigned long *REGISTER;
 
REGISTER mc_poc        = (unsigned long*)(MC_BASE + MC_POC);
REGISTER mc_csr        = (unsigned long*)(MC_BASE + MC_CSR);
REGISTER mc_ba_mask    = (unsigned long*)(MC_BASE + MC_BA_MASK);
 
unsigned long lpoc;
 
unsigned long set_config()
{
    REGISTER mc_csc;
    unsigned char ch;
 
    lpoc = *mc_poc;
 
    for (ch=0; ch<8; ch++) {
        if (MC_ASYNC_CSMASK & (0x01 << ch) ) {
	    mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
	    SET_FIELD(*mc_csc, MC_CSC, SEL, mc_async_cs[ch].M);
	    SET_FIELD(*mc_csc, MC_CSC, BW,  mc_async_cs[ch].BW);
	    SET_FLAG(*mc_csc, MC_CSC, EN);
	    printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
	}
    }
 
    return 0;
}
 
int main()
{
    unsigned long ret;
    unsigned char ch;
 
    unsigned long test;
 
    unsigned long nAddress;
    unsigned long nMemSize;
    unsigned long mc_sel;
    REGISTER mc_tms;
    REGISTER mc_cs;
 
    /* set configuration */
    /* MC initialization done in except_mc.S prior to execution of main() 
    if ( (ret = set_config()) != 0) { 
	exit(ret); 
    } 
    */
 
    for (ch=0; ch<8; ch++) {
	if (MC_ASYNC_CSMASK & (0x01 << ch) ) {
	    printf ("--- Begin Test on CS%d ---\n", ch);
 
	    mc_cs  = (unsigned long*)(MC_BASE + MC_CSC(ch));
	    mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
	    mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
 
	    printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
		    *mc_cs, *mc_tms);
 
	    for (test=0; test<4; test++) {
		/* configure MC*/
		CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
		CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
		CLEAR_FLAG(*mc_cs, MC_CSC, WP);  /* write enable */
 
		switch (test) {
		case 0:
		    if ((MC_ASYNC_TESTS & MC_ASYNC_TEST0) != MC_ASYNC_TEST0)
			continue;
		    break;
		case 1:
		    if ((MC_ASYNC_TESTS & MC_ASYNC_TEST1) != MC_ASYNC_TEST1)
			continue;
		    SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
		    break;
		case 2:
		    if ((MC_ASYNC_TESTS & MC_ASYNC_TEST2) != MC_ASYNC_TEST2)
			continue;
		    SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row */
		    break;
		case 3:
		    if ((MC_ASYNC_TESTS & MC_ASYNC_TEST3) != MC_ASYNC_TEST3)
			continue;
		    SET_FLAG(*mc_cs, MC_CSC, WP);  /* RO */
		    break;
		} /*switch test*/
 
		printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
 
		nAddress = mc_sel << 21;
		nAddress |= MC_MEM_BASE;
		nMemSize = ( ((*mc_ba_mask & 0x000000FF) + 1) << 21);
		ret = mc_test_row(nAddress, nAddress + nMemSize, MC_ASYNC_FLAGS);
 
		printf("\trow tested: nAddress = 0x%08lX, ret = 0x%08lX\n", nAddress, ret);
 
		if (ret) {
		    return ret;
		}
 
	    } /*for test*/
	} /*if*/
    } /*for CS*/
    printf("--- End ASYNC tests ---\n");
    return 0;
} /* main */