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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ROM Controller for Coregen ROM block                        ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Manages access from Wishbone to internal ROM                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, jcastillo@opensocdesign.com          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module wb_rom_controller(clk,reset,
 
                         wb_stb_i,wb_dat_o,wb_dat_i,
                         wb_ack_o,wb_adr_i,wb_we_i,
                         wb_cyc_i,wb_sel_i,
 
                         address,data
                        );
 
input         clk;
input         reset;
 
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [31:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
 
output [14:0] address;
input  [31:0] data;
 
reg  [31:0]  wb_dat_o;
reg          wb_ack_o;
reg  [14:0]  address;
 
reg        next_reading;
reg        reading;
 
 
//read_data:
always @(posedge clk or posedge reset)
begin
   if(reset==1)
   begin
     wb_ack_o<=#1 1'b0;
     wb_dat_o<=#1 1'b0;
   end
   else
   begin
     wb_dat_o <= #1 1'b0;
     wb_ack_o <= #1 1'b0;
     if (reading)
     begin
       wb_ack_o <= #1 1'b1;
       wb_dat_o <= #1 data;
     end
  end
end
 
reg [31:0] addr_var;
 
always @(wb_adr_i or wb_stb_i or wb_we_i or wb_cyc_i
         or reading or wb_ack_o)
 
   begin
 
   next_reading  = 1'b0;
 
   addr_var = wb_adr_i >> 2;
   address  = addr_var[14:0];   
 
   if(~reading && ~wb_ack_o) 
   begin
 
     if (wb_cyc_i && wb_stb_i && !wb_we_i)
     begin
       addr_var = wb_adr_i >> 2;
       address  = addr_var[14:0];   
       next_reading  = 1'b1;
     end
 
   end
   if(reading)
     next_reading=1'b0;
 
 end
 
 
//register_proc:
always @(posedge clk or posedge reset)
 
   begin
 
   if (reset )
      begin
      reading  <= #1 1'b0;
      end
   else 
      begin
      reading  <= #1 next_reading;
      end
   end
 
endmodule