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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's simulation monitor                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Simulation monitor                                          ////
////                                                              ////
////  To Do:                                                      ////
////   - move it to bench                                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/20 18:17:52  damjan
// Initial revision
//
// Revision 1.1  2001/08/13 03:37:07  lampret
// Added monitor.v and timescale.v
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "defines.v"
 
// Enable debug_mem task. Only affects simulation.
`define enable_debug_mem
 
// Enable display_arch_state task. Only affects simulation.
`define enable_display_arch_state
 
module or1200_monitor;
 
task monitortask;
begin
end
endtask
 
integer fexe;
reg [23:0]  ref;
 
initial begin
	ref = 0;
	fexe = $fopen("executed.log");
	$timeformat (-9, 2, " ns", 12);
end
 
task finish_simulation;
begin
	$fclose(fexe);
	display_arch_state;
	display_memory(0, 8191);
        $shm_save;
        $shm_close;
        $dumpflush;
	$finish;
end
endtask
 
task caught_sys203;
begin
	$display("simulation terminated due to l.sys 203");
	finish_simulation;
end
endtask
 
task display_arch_state;
reg [5:0] i;
reg [31:0] r;
integer	j;
begin
`ifdef enable_display_arch_state
	ref = ref + 1;
//	if (ref == 17890) begin
//		$dumpfile("dump.vcd");
//		$dumpvars(20,tb_or1200);
//	end
	$fwrite(fexe, "\nEXECUTED(): %h:  %h", xess_top.i_xess_fpga.risc.cpu.except.wb_pc, xess_top.i_xess_fpga.risc.cpu.id.wb_insn);
	for(i = 0; i < 32; i = i + 1) begin
		if (i % 4 == 0)
			$fdisplay(fexe);
`ifdef XILINX_RAMB4
		r = 32'h0000_0000;
		for(j = 0; j < 16; j = j + 1) begin
			r[j] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_0.mem[i*16+j];
		end
		for(j = 0; j < 16; j = j + 1) begin
			r[j+16] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_1.mem[i*16+j];
		end
		$fwrite(fexe, "GPR%d: %h  ", i, r);
`else
`ifdef XILINX_RAM32X1D
`else
`ifdef ARTISAN_SDP
`else
		$fwrite(fexe, "GPR%d: %h  ", i, xess_top.i_xess_fpga.risc.cpu.rf.rf_a.mem[i]);
`endif
`endif
`endif
	end
	$fdisplay(fexe);
	r = xess_top.i_xess_fpga.risc.cpu.sprs.sr;
	$fwrite(fexe, "SR   : %h  ", r);
	r = xess_top.i_xess_fpga.risc.cpu.sprs.epcr;
	$fwrite(fexe, "EPCR0: %h  ", r);
	r = xess_top.i_xess_fpga.risc.cpu.sprs.eear;
	$fwrite(fexe, "EEAR0: %h  ", r);
	r = xess_top.i_xess_fpga.risc.cpu.sprs.esr;
	$fdisplay(fexe, "ESR0 : %h", r);
//	$fdisplay(fexe);
`endif
end
endtask
 
task display_memory;
input [31:0] from;
input [31:0] to;
integer i;
begin
//	for(i = from; i < to; i = i + 4)
//		$display("mem[%h] = %h   mem[%h] = %h   mem[%h] = %h   mem[%h] = %h ",
//		i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32
//		i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32
end
endtask
 
task debug_mem;
input [79:0] device;
input write;
input [31:0] addr;
input [31:0] data;
input [3:0] bs;
begin
`ifdef enable_debug_mem
	if (write)
		$display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
	else
		$display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
`endif
end
endtask
 
always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
	if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
		#2;
		if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
			&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
			display_arch_state;
		if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb)  // small hack to stop simulation (l.sys 203)
			caught_sys203;
	end
 
endmodule