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[/] [or1k/] [tags/] [first/] [mp3/] [sim/] [run/] [run_sim] - Rev 1765
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#!/bin/csh -f
ncprep -f ../bin/nc.scr
#debussy -f ../bin/nc.scr
#nLint -f ../bin/nc.scr
#verilog -f ../bin/nc.scr
# mv ncverilog.log ../log/ncverilog.log
ncvlog -f ncvlog.args
if ($status != 0) then
exit
endif
# Run the NC-Verilog elaborator (build the design hierarchy)
ncelab -f ncelab.args
if ($status != 0) then
exit
endif
# Run the NC-Verilog simulator (simulate the design)
ncsim -f ncsim.args && \
mv flash.log ../log && \
mv executed.log ../log && \
mv sram.log ../log