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[/] [or1k/] [tags/] [nog_patch_33/] [or1ksim/] [testbench/] [mmu.c] - Rev 410
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/* This is MMU test for OpenRISC 1200 */ #include "spr_defs.h" #include "support.h" /* Define RAM physical location and size Bottom half will be used for this program, the rest will be used for testing */ #define RAM_START 0x40000000 #define RAM_SIZE 0x00200000 /* What is the last address in ram that is used by this program */ #define CODE_END_ADD (RAM_START + (RAM_SIZE / 2)) /* MMU page size */ #define PAGE_SIZE 4096 /* Number of DTLB sets used (power of 2, max is 256) */ #define DTLB_SETS 16 /* Number of DTLB ways (1, 2, 3 etc., max is 4). */ #define DTLB_WAYS 2 /* Number of ITLB sets used (power of 2, max is 256) */ #define ITLB_SETS 16 /* Number of ITLB ways (1, 2, 3 etc., max is 4). */ #define ITLB_WAYS 2 /* TLB mode codes */ #define TLB_CODE_ONE_TO_ONE 0x00000000 #define TLB_CODE_PLUS_ONE_PAGE 0x10000000 #define TLB_CODE_MINUS_ONE_PAGE 0x20000000 #define TLB_CODE_MASK 0xfffff000 #define TLB_PR_MASK 0x00000fff /* Extern functions */ extern void lo_dmmu_en (void); extern void lo_immu_en (void); /* Global variables */ extern unsigned long ram_end; /* DTLB mode status */ unsigned long dtlb_val; /* ITLB mode status */ unsigned long itlb_val; /*inline static unsigned int dtlb_write_entry (int way, int entry, unsigned int val) { mtspr (SPR_DTLBMR_BASE(way) + entry, val); } */ /* DTLB miss exception handler */ void dtlb_miss_handler (void) { unsigned long ea, ta, tlbtr; int set, way = 0; int i; /* Get EA that cause the exception */ ea = mfspr (SPR_EEAR_BASE); printf("ea = %.8lx\n", ea); /* Find TLB set and LRU way */ set = (ea / PAGE_SIZE) % DTLB_SETS; for (i = 0; i < DTLB_WAYS; i++) { if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) { way = i; break; } } printf("set = %.8lx\n", set); if (RAM_START < ea < CODE_END_ADD) { printf("RAM_START< ea < CODE_END_ADD\n", ea); /* If this is acces to data of this program set one to one translation */ mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V); mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | SPR_DTLBTR_CI | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | SPR_DTLBTR_SWE); return; } /* Whatever access is in progress, translated address have to point to physical RAM */ ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START; /* Set appropriate TLB entry */ switch (dtlb_val & TLB_CODE_MASK) { case TLB_CODE_ONE_TO_ONE: tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK); break; case TLB_CODE_PLUS_ONE_PAGE: if ((ta + PAGE_SIZE) >= (RAM_START + RAM_SIZE)) /* Wrapp last page */ tlbtr = (((ta & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK); else tlbtr = ((ta + PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK); break; case TLB_CODE_MINUS_ONE_PAGE: if ((ta - PAGE_SIZE) < (RAM_START + (RAM_SIZE/2))) /* Wrapp first page */ tlbtr = ((ta - PAGE_SIZE + (RAM_SIZE/2)) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK); else tlbtr = ((ta - PAGE_SIZE) & SPR_DTLBTR_PPN) | (dtlb_val | TLB_PR_MASK); break; } /* Set DTLB entry */ mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V); mtspr (SPR_DTLBTR_BASE(way) + set, tlbtr); } /* ITLB miss exception handler */ void itlb_miss_handler (void) { } /* Invalidate all entries in DTLB and enable DMMU */ void dmmu_enable (void) { int i, j; /* Invalidate all entries in DTLB */ for (i = 0; i < DTLB_WAYS; i++) { for (j = 0; j < DTLB_SETS; j++) { mtspr (SPR_DTLBMR_BASE(i) + j, 0); mtspr (SPR_DTLBTR_BASE(i) + j, 0); } } /* Register DTLB miss handler */ excpt_dtlbmiss = (unsigned long)dtlb_miss_handler; /* Enable DMMU */ lo_dmmu_en (); } /* Invalidate all entries in ITLB and enable IMMU */ void immu_enable (void) { int i, j; /* Invalidate all entries in ITLB */ for (i = 0; i < ITLB_WAYS; i++) { for (j = 0; j < ITLB_SETS; i++) { mtspr (SPR_ITLBMR_BASE(i) + j, 0); mtspr (SPR_ITLBTR_BASE(i) + j, 0); } } /* Register ITLB miss handler */ excpt_itlbmiss = (unsigned long)itlb_miss_handler; /* Enable IMMU */ lo_immu_en (); } void write_pattern(unsigned long start, unsigned long end) { unsigned long add; add = start; while (add < end) { REG32(add) = add; add += PAGE_SIZE; } } int main (void) { dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | SPR_DTLBTR_SWE; /* Enable DMMU */ dmmu_enable(); /* Write pattern */ write_pattern(0x40000000, 0x40100000); /* Enable IMMU */ // immu_enable(); exit(0); return 0; }
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