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/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This file is also used by microkernel test bench. Among
others it is also used in assembly file(s). */
 
/* Definition of special-purpose registers (SPRs) */
 
#define MAX_GRPS 32
#define MAX_SPRS_PER_GRP 0x1000
#define MAX_SPRS (MAX_GRPS * 0x1000000 / MAX_SPRS_PER_GRP)
 
/* Base addresses for the groups */
#define SPRGROUP_SYS	0x00000000
#define SPRGROUP_DMMU	0x01000000
#define SPRGROUP_IMMU	0x02000000
#define SPRGROUP_DC	0x03000000
#define SPRGROUP_IC	0x04000000
#define SPRGROUP_MAC	0x05000000
#define SPRGROUP_TT	0x09000000
 
/* System control and status group */
#define SPR_VR		(SPRGROUP_SYS + 0)
#define SPR_MPR		(SPRGROUP_SYS + 1)
#define SPR_SR		(SPRGROUP_SYS + 2)
#define SPR_EPCR_BASE	(SPRGROUP_SYS + 16)
#define SPR_EPCR_LAST	(SPRGROUP_SYS + 31)
#define SPR_CTR_BASE	(SPRGROUP_SYS + 32)
#define SPR_CTR_LAST	(SPRGROUP_SYS + 47)
#define SPR_EEAR_BASE	(SPRGROUP_SYS + 48)
#define SPR_EEAR_LAST	(SPRGROUP_SYS + 63)
#define SPR_ESR_BASE	(SPRGROUP_SYS + 64)
#define SPR_ESR_LAST	(SPRGROUP_SYS + 79)
 
/* Data MMU group */
#define SPR_DMMUCR	(SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY)	(SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
#define SPR_DTLBMR_LAST(WAY)	(SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
#define SPR_DTLBTR_BASE(WAY)	(SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
#define SPR_DTLBTR_LAST(WAY)	(SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
 
/* Instruction MMU group */
#define SPR_IMMUCR	(SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY)	(SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
#define SPR_ITLBMR_LAST(WAY)	(SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
#define SPR_ITLBTR_BASE(WAY)	(SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
#define SPR_ITLBTR_LAST(WAY)	(SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
 
/* Data cache group */
#define SPR_DCCR	(SPRGROUP_DC + 0)
#define SPR_DCR_BASE(WAY)	(SPRGROUP_DC + 0x200 + (WAY) * 0x200)
#define SPR_DCR_LAST(WAY)	(SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
 
/* Instruction cache group */
#define SPR_ICCR	(SPRGROUP_IC + 0)
#define SPR_ICR_BASE(WAY)	(SPRGROUP_IC + 0x200 + (WAY) * 0x200)
#define SPR_ICR_LAST(WAY)	(SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
 
/* MAC group */
#define SPR_MACLO (SPRGROUP_MAC + 1)
#define SPR_MACHI (SPRGROUP_MAC + 2)
 
/* Tick Timer group */
#define SPR_TTCR (SPRGROUP_TT + 0)
#define SPR_TTIR (SPRGROUP_TT + 1)
 
/*
 * Bit definitions for the Version Register
 *
 */
#define SPR_VR_VER	0xffff0000  /* Processor version */
#define SPR_VR_PT	0x0000f000  /* Predefined template */
#define SPR_VR_REV	0x0000003f  /* Processor revision */
 
/*
 * Bit definitions for the Module Present Register
 *
 */
#define SPR_MPR_SYS	0x00000001  /* System control and status module */
#define SPR_MPR_DMMU	0x00000002  /* Data MMU module */
#define SPR_MPR_IMMU	0x00000004  /* Instruction MMU module */
#define SPR_MPR_DC	0x00000008  /* Data cache module */
#define SPR_MPR_IC	0x00000010  /* Instruction cache module */
#define SPR_MPR_MAC	0x00000020  /* MAC module */
#define SPR_MPR_RES	0xffffffc0  /* Custom and future modules */
 
/*
 * Bit definitions for the Supervision Register
 *
 */
#define SPR_SR_CID	0xf0000000  /* Context ID */
#define SPR_SR_CF	0x00000100  /* Condition Flag */
#define SPR_SR_LEE	0x00000080  /* Little Endian Enable */
#define SPR_SR_IME	0x00000040  /* Instruction MMU Enable */
#define SPR_SR_DME	0x00000020  /* Data MMU Enable */
#define SPR_SR_ICE	0x00000010  /* Instruction Cache Enable */
#define SPR_SR_DCE	0x00000008  /* Data Cache Enable */
#define SPR_SR_EIR	0x00000004  /* External Interrupt Recognition */
#define SPR_SR_EXR	0x00000002  /* Exception Recognition */
#define SPR_SR_SUPV	0x00000001  /* Supervisor mode */
 
/*
 * Bit definitions for the Condition Code Register
 *
 */
#define SPR_CCR_OVERFL	0x00000004  /* Overflow */
#define SPR_CCR_CARRY	0x00000002  /* Carry */
#define SPR_CCR_FLAG	0x00000001  /* Compare Flag */
 
/*
 * Bit definitions for the Data MMU Control Register
 *
 */
#define SPR_DMMUCR_P2S	0x0000003e  /* Level 2 Page Size */
#define SPR_DMMUCR_P1S	0x000007c0  /* Level 1 Page Size */
#define SPR_DMMUCR_VADDR_WIDTH	0x0000f800  /* Virtual ADDR Width */
#define SPR_DMMUCR_PADDR_WIDTH	0x000f0000  /* Physical ADDR Width */
 
/*
 * Bit definitions for the Instruction MMU Control Register
 *
 */
#define SPR_IMMUCR_P2S	0x0000003e  /* Level 2 Page Size */
#define SPR_IMMUCR_P1S	0x000007c0  /* Level 1 Page Size */
#define SPR_IMMUCR_VADDR_WIDTH	0x0000f800  /* Virtual ADDR Width */
#define SPR_IMMUCR_PADDR_WIDTH	0x000f0000  /* Physical ADDR Width */
 
/*
 * Bit definitions for the Data TLB Match Register
 *
 */
#define SPR_DTLBMR_V	0x00000001  /* Valid */
#define SPR_DTLBMR_PL1	0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID	0x0000003c  /* Context ID */
#define SPR_DTLBMR_LRU	0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_VPN	0xfffff000  /* Virtual Page Number */
 
/*
 * Bit definitions for the Data TLB Translate Register
 *
 */
#define SPR_DTLBTR_CC	0x00000001  /* Cache Coherency */
#define SPR_DTLBTR_CI	0x00000002  /* Cache Inhibit */
#define SPR_DTLBTR_WBC	0x00000004  /* Write-Back Cache */
#define SPR_DTLBTR_WOM	0x00000008  /* Weakly-Ordered Memory */
#define SPR_DTLBTR_A	0x00000010  /* Accessed */
#define SPR_DTLBTR_D	0x00000020  /* Dirty */
#define SPR_DTLBTR_URE	0x00000040  /* User Read Enable */
#define SPR_DTLBTR_UWE	0x00000080  /* User Write Enable */
#define SPR_DTLBTR_SRE	0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE	0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN	0xfffff000  /* Physical Page Number */
 
/*
 * Bit definitions for the Instruction TLB Match Register
 *
 */
#define SPR_ITLBMR_V	0x00000001  /* Valid */
#define SPR_ITLBMR_PL1	0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID	0x0000003c  /* Context ID */
#define SPR_ITLBMR_LRU	0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_VPN	0xfffff000  /* Virtual Page Number */
 
/*
 * Bit definitions for the Instruction TLB Translate Register
 *
 */
#define SPR_ITLBTR_CC	0x00000001  /* Cache Coherency */
#define SPR_ITLBTR_CI	0x00000002  /* Cache Inhibit */
#define SPR_ITLBTR_WBC	0x00000004  /* Write-Back Cache */
#define SPR_ITLBTR_WOM	0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A	0x00000010  /* Accessed */
#define SPR_ITLBTR_D	0x00000020  /* Dirty */
#define SPR_ITLBTR_URE	0x00000040  /* User Read Enable */
#define SPR_ITLBTR_UWE	0x00000080  /* User Write Enable */
#define SPR_ITLBTR_SRE	0x00000100  /* Supervisor Read Enable */
#define SPR_ITLBTR_SWE	0x00000200  /* Supervisor Write Enable (not used actually) */
#define SPR_ITLBTR_PPN	0xfffff000  /* Physical Page Number */
 
/*
 * Bit definitions for Tick Timer Control Register
 *
 */
#define SPR_TTCR_PERIOD	0x0fffffff  /* Time Period */
#define SPR_TTCR_IP	0x10000000  /* Interrupt Present */
#define SPR_TTCR_IE	0x20000000  /* Interrupt Enable */
#define SPR_TTCR_SR	0x40000000  /* Single Run */
#define SPR_TTCR_TTE	0x80000000  /* Tick Timer Enable */