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[/] [or1k/] [tags/] [nog_patch_46/] [or1ksim/] [sim.cfg] - Rev 262
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section memory
memory_table_file = "simmem.cfg"
random_seed = 12345
type = random
end
section mc
enabled = 1
baseaddr = 0xa0000000
POC = 0x00000008 /* Power on configuration register */
end
section uart
enabled = 1
nuarts = 1
device 0
baseaddr = 0x80000000
rxfile = "/tmp/uart0.rx"
txfile = "/tmp/uart0.tx"
jitter = -1 /* async behaviour */
enddevice
end
section dma
enabled = 1
ndmas = 1
device 0
baseaddr = 0x90000000
irq = 4
enddevice
end
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