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/* except.c -- Simulation of OR1K exceptions
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "abstract.h"
#include "except.h"
#include "sprs.h"
 
extern int cont_run;
extern struct iqueue_entry iqueue[20];
extern unsigned long pc;
extern unsigned long pcnext;
extern unsigned long pc_phy;
extern struct iqueue_entry iqueue[];
 
extern int delay_insn;
int cycle_delay = 0;  /* Added by CZ 27/05/01 */
 
/* Handle OR1K exceptions. */
void except_handle(int except, unsigned long ea)
{
	unsigned long pc_saved;
 
	printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
	printf("Iqueue[0].insn_addr: 0x%x  Eff ADDR: 0x%x\n",  iqueue[0].insn_addr, ea);
	printf("  pc: 0x%x  pcnext: 0x%x\n",  pc, pcnext);
 
#if ONLY_VIRTUAL_MACHINE
	printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
	cont_run = 0;
#else
 
	if (delay_insn) {
		printf(" INFO: Exception during execution of delay slot insn.\n");
		pc -= 4;
	}
#if 0
	if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) {	/* Always execute delay slot insn */
		printf("XXXXXXXXXXXXXX\n");
		fetch();						/* before starting with exception */
		decode(&iqueue[0]);					/* (itlbmiss is special case) */
		execute();                                        
	}
#endif
 
	if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
		printf("ABORT: Exception occured while exception detection was disabled.\n");
		cont_run = 0;
		return;
	}
 
	pc_saved = pc & ~0x3;
	mtspr(SPR_EPCR_BASE, pc_saved);
	mtspr(SPR_EEAR_BASE, ea);
	mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
 
	/* Address translation is always disabled when starting exception. */
	mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
	mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
 
	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);	/* SUPV mode */
	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR);	/* Disable except. */
	pc = (unsigned long)except;
 
	/* MM: We do pc update after the execute (in the simulator), so we
	   decrease it by 4 so that next instruction points to first exception
	   instruction. */
	if (except == EXCEPT_SYSCALL)
	  pc -= 4;
	pcnext = pc+4;	
 
	/* Added by CZ 27/05/01 */
	pc_phy = pc;
	cycle_delay = 7;  /* An exception stalls the CPU 7 clock cycles */
#endif
}