URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [or32/] [execute.c] - Rev 600
Go to most recent revision | Compare with Previous | Blame | View Log
/* execute.c -- OR1K architecture dependent simulation Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Most of the OR1K simulation is done in here. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <ctype.h> #include "config.h" #include "arch.h" #include "opcode/or32.h" #include "branch_predict.h" #include "abstract.h" #include "labels.h" #include "parse.h" #include "execute.h" #include "stats.h" #include "except.h" #include "sprs.h" #include "sim-config.h" #include "debug_unit.h" /* General purpose registers. */ machword reg[MAX_GPRS]; /* Instruction queue */ struct iqueue_entry iqueue[20]; /* Is current insn in execution a delay insn? */ int delay_insn; /* Benchmark multi issue execution */ int multissue[20]; int supercycles; int issued_per_cycle = 4; int hazardwait = 0; /* Whether break was hit - so we can step over a break */ static int break_just_hit = 0; /* freemem 'pointer' */ extern unsigned long freemem; /* Completition queue */ struct iqueue_entry icomplet[20]; /* Program counter (and translated PC) */ unsigned long pc; unsigned long pc_phy; /* Previous program counter */ unsigned long pcprev = 0; /* Temporary program counter */ unsigned long pcnext; /* Delay instruction effective address register */ unsigned long pcdelay; /* CCR */ int flag; /* CCR (for dependency calculation) */ char ccr_flag[10] = "flag"; /* Cycles counts fetch stages */ int cycles; /* Each cycle has counter of mem_cycles; this value is joined with cycles at the end of the cycle; no sim originated memory accesses should be performed inbetween. */ int mem_cycles; /* Instructions executed */ int instructions; /* Load and store stalls */ int loadcycles, storecycles; /* Local data needed for execution. */ static struct iqueue_entry *cur; static int next_delay_insn; static int breakpoint; static unsigned long *op; static int num_op; /* Implementation specific. Get an actual value of a specific register. */ unsigned long evalsim_reg32(int regno) { if (regno < MAX_GPRS) { return reg[regno]; } else { printf("\nABORT: read out of registers\n"); cont_run = 0; return 0; } } /* Implementation specific. Set a specific register with value. */ void setsim_reg32(int regno, unsigned long value) { if (regno == 0) /* gpr0 is always zero */ value = 0; if (regno < MAX_GPRS) { reg[regno] = value; } else { printf("\nABORT: write out of registers\n"); cont_run = 0; } } /* Implementation specific. Get an actual value of a specific register. */ inline static unsigned long eval_reg32(int regno) { if (regno < MAX_GPRS) { IFF(config.cpu.raw_range) { int delta = (cycles - raw_stats.reg[regno]); if (delta < config.cpu.raw_range) raw_stats.range[delta]++; } debug(9, "atoi ret1\n"); return reg[regno]; } else { printf("\nABORT: read out of registers\n"); cont_run = 0; return 0; } } /* Implementation specific. Set a specific register with value. */ inline static void set_reg32(int regno, unsigned long value) { #if 0 if (strcmp(regstr, FRAME_REG) == 0) { printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc); printf("Old:%.8lx New:%.8lx\n", eval_reg(regno), value); } if (strcmp(regstr, STACK_REG) == 0) { printf("SP (%s) modified by insn at %x. ", STACK_REG, pc); printf("Old:%.8lx New:%.8lx\n", eval_reg(regmo), value); } #endif if (regno < MAX_GPRS) { reg[regno] = value; IFF(config.cpu.raw_range) raw_stats.reg[regno] = cycles; } else { printf("\nABORT: write out of registers\n"); cont_run = 0; } } /* Does srcoperand depend on computation of dstoperand? Return non-zero if yes. Cycle t Cycle t+1 dst: irrelevant src: immediate always 0 dst: reg1 direct src: reg2 direct 0 if reg1 != reg2 dst: reg1 disp src: reg2 direct always 0 dst: reg1 direct src: reg2 disp 0 if reg1 != reg2 dst: reg1 disp src: reg2 disp always 1 (store must finish before load) dst: flag src: flag always 1 */ int depend_operands(prev, next) struct iqueue_entry *prev; struct iqueue_entry *next; { /* Find destination type. */ unsigned long type = 0; int i = 0; if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG && or32_opcodes[next->insn_index].flags & OR32_R_FLAG) return 1; while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST)) if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST) { type = prev->op[i + MAX_OPERANDS]; break; } else i++; /* We search all source operands - if we find confict => return 1 */ i = 0; while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST)) if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST)) { if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS) if (type & OPTYPE_DIS) return 1; else if (next->op[i] == prev->op[i] && (next->op[i + MAX_OPERANDS] & OPTYPE_REG)) return 1; if (next->op[i] == prev->op[i] && (next->op[i + MAX_OPERANDS] & OPTYPE_REG) && (type & OPTYPE_REG)) return 1; i++; } else i++; return 0; } /* Implementation specific. Parses and returns operands. */ static void eval_operands (unsigned long insn, int insn_index, int* breakpoint) { struct insn_op_struct *opd = op_start[insn_index]; unsigned long data = 0; int dis = 0; int no = 0; while (1) { unsigned long tmp = 0, nbits = 0; while (1) { tmp |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits; nbits += opd->data; if (opd->type & OPTYPE_OP) break; opd++; } /* Do we have to sign extend? */ if (opd->type & OPTYPE_SIG) { int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; if (tmp & (1 << sbit)) tmp |= 0xFFFFFFFF << sbit; } if (opd->type & OPTYPE_DIS) { /* We have to read register later. */ data += tmp; dis = 1; } else { if (dis && (opd->type & OPTYPE_REG)) op[no] = data + eval_reg32 (tmp); else op[no] = tmp; op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0); no++; data = 0; dis = 0; } if(opd->type & OPTYPE_LAST) return; opd++; } num_op = no; } /* Implementation specific. Evaluates source operand op_no. */ inline static unsigned long eval_operand32 (int op_no, int *breakpoint) { debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]); if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) /* memory accesses are not cached */ return eval_mem32 (op[op_no], breakpoint); else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) { return eval_reg32 (op[op_no]); } else { return op[op_no]; } } /* Implementation specific. Evaluates source operand op_no. */ static unsigned long eval_operand16 (int op_no, int *breakpoint) { debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]); if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) { return eval_mem16 (op[op_no], breakpoint); } else { fprintf (stderr, "Invalid operand type.\n"); exit (1); } } /* Implementation specific. Evaluates source operand op_no. */ static unsigned long eval_operand8 (int op_no, int *breakpoint) { debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]); if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) return eval_mem8 (op[op_no], breakpoint); else { fprintf (stderr, "Invalid operand type.\n"); exit (1); } } /* Implementation specific. Set destination operand (register direct, register indirect (with displacement) with value. */ inline static void set_operand32(int op_no, unsigned long value, int* breakpoint) { /* Mark this as destination operand. */ IFF (config.cpu.dependstats) op[op_no + MAX_OPERANDS] |= OPTYPE_DST; if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) { set_mem32(op[op_no], value, breakpoint); } else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) { set_reg32(op[op_no], value); /* TODO: OV incorrect */ value & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0); } else { fprintf (stderr, "Invalid operand type.\n"); exit (1); } } /* Implementation specific. Set destination operand (register direct, register indirect (with displacement) with value. */ void set_operand16(int op_no, unsigned long value, int* breakpoint) { /* Mark this as destination operand. */ op[op_no + MAX_OPERANDS] |= OPTYPE_DST; if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) { set_mem16(op[op_no], value, breakpoint); } else { fprintf (stderr, "Invalid operand type.\n"); exit (1); } } /* Implementation specific. Set destination operand (register direct, register indirect (with displacement) with value. */ void set_operand8(int op_no, unsigned long value, int* breakpoint) { /* Mark this as destination operand. */ op[op_no + MAX_OPERANDS] |= OPTYPE_DST; if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) set_mem8(op[op_no], value, breakpoint); else { fprintf (stderr, "Invalid operand type.\n"); exit (1); } } /* Modified by CZ 26/05/01 for new mode execution */ /* Fetch returns nonzero if instruction should NOT be executed. */ static inline int fetch() { struct mem_entry *entry; debug(5, "fetch()\n"); /* Update the pc for pending exceptions, or get physical pc */ if (!pending.valid) pc_phy = translate_vrt_to_phy_add(pc); if(pending.valid) except_handle_backend(pending.type, pending.address, pending.saved); if (CHECK_BREAKPOINTS) { /* MM: Check for breakpoint. This has to be done in fetch cycle, because of peripheria. MM1709: if we cannot access the memory entry, we could not set the breakpoint earlier, so just chech the breakpoint list. */ if (has_breakpoint (pc_phy) && !break_just_hit) { break_just_hit = 1; return 1; /* Breakpoint set. */ } break_just_hit = 0; } instructions++; pc_phy &= ~0x03; /* Fetch instruction. */ iqueue[0].insn_addr = pc; iqueue[0].insn = eval_insn (pc_phy, &breakpoint);; /* update_pc will be called after execution */ return 0; } /* This code actually updates the PC value. */ static inline void update_pc() { pcprev = pc; /* Store value for later */ pc = pcnext; pcnext = delay_insn ? pcdelay : pcnext + 4; } static inline void analysis() { if (config.cpu.dependstats) /* Instruction waits in completition buffer until retired. */ memcpy (&icomplet[0], &iqueue[0], sizeof (struct iqueue_entry)); if (config.sim.history) { int i; /* History of execution */ for (i = HISTEXEC_LEN - 1; i; i--) histexec[i] = histexec[i - 1]; histexec[0] = icomplet[0].insn_addr; /* add last insn */ } } /* Execution logger. */ inline void dump_exe_log() { unsigned long i = iqueue[0].insn_addr; if (i == 0xffffffff) return; fprintf(runtime.sim.fexe_log, "\nEXECUTED(): %.8lx: ", i); fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1)); fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3)); for(i = 0; i < MAX_GPRS; i++) { if (i % 4 == 0) fprintf(runtime.sim.fexe_log, "\n"); fprintf(runtime.sim.fexe_log, "GPR%2u: %.8lx ", i, reg[i]); } fprintf(runtime.sim.fexe_log, "\n"); fprintf(runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR)); fprintf(runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE)); fprintf(runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE)); fprintf(runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE)); } #if 0 void print_time (int cycles, char *output) { int i = 0, c_ps = config.sim.clkcycle_ps; while (c_ps % 1000 == 0 && i < 2) { c_ps /= 1000; i++; } c_ps *= cycles; sprintf (output, "%i%cs", cycles, i == 0 ? 'p' : i == 1 ? 'n': 'u'); } #endif void dumpreg() { int i; char temp[100]; dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4, 1, 0); generate_time_pretty (temp, cycles); printf(" (executed) [time %s, #%i]\n", temp, instructions); if (config.cpu.superscalar) printf ("Superscalar CYCLES: %u", supercycles); if (config.cpu.hazards) printf (" HAZARDWAIT: %u\n", hazardwait); else if (config.cpu.superscalar) printf ("\n"); dumpmemory(pc, pc + 4, 1, 0); printf(" (next insn) %s", (delay_insn?"(delay insn)":"")); for(i = 0; i < MAX_GPRS; i++) { if (i % 4 == 0) printf("\n"); printf("GPR%.2u: %.8lx ", i, evalsim_reg32(i)); } printf("flag: %u\n", flag); } /* Address calculation changed by CZ on 27/05/01 */ static inline void decode_execute(struct iqueue_entry *current) { int insn_index; next_delay_insn = 0; breakpoint = 0; if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy)) breakpoint++; IFF (config.cpu.dependstats) current->func_unit = it_unknown; current->insn_index = insn_index = insn_decode(current->insn); #ifndef HAS_EXECUTION #error HAS_EXECUTION has to be defined in order to execute programs. #endif cur = current; /* globals; needed by eval/set_operand */ if (insn_index < 0) l_invalid(); else { op = &cur->op[0]; eval_operands (cur->insn, insn_index, &breakpoint); or32_opcodes[insn_index].exec(); } /* Check for range exception */ if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV)) except_handle (EXCEPT_RANGE, 0); if (config.cpu.dependstats) { iqueue[0].insn_index = insn_index; /* Dynamic, dependency stats. */ adddstats(icomplet[0].insn_index, iqueue[0].insn_index, 1, check_depend()); /* Dynamic, functional units stats. */ addfstats(icomplet[0].func_unit, iqueue[0].func_unit, 1, check_depend()); /* Dynamic, single stats. */ addsstats(iqueue[0].insn_index, 1); } if (config.cpu.superscalar) { if ((cur->func_unit == it_branch) || (cur->func_unit == it_jump)) storecycles += 0; if (cur->func_unit == it_store) storecycles += 1; if (cur->func_unit == it_load) loadcycles += 1; #if 0 if ((icomplet[0].func_unit == it_load) && check_depend()) loadcycles++; #endif /* Pseudo multiple issue benchmark */ if ((multissue[cur->func_unit] < 1) || (check_depend()) || (issued_per_cycle < 1)) { int i; for (i = 0; i < 20; i++) multissue[i] = 2; issued_per_cycle = 2; supercycles++; if (check_depend()) hazardwait++; multissue[it_unknown] = 2; multissue[it_shift] = 2; multissue[it_compare] = 1; multissue[it_branch] = 1; multissue[it_jump] = 1; multissue[it_extend] = 2; multissue[it_nop] = 2; multissue[it_move] = 2; multissue[it_movimm] = 2; multissue[it_arith] = 2; multissue[it_store] = 2; multissue[it_load] = 2; } multissue[cur->func_unit]--; issued_per_cycle--; } delay_insn = next_delay_insn; if(breakpoint) except_handle(EXCEPT_TRAP, 0); } void cpu_reset() { cycles = 0; instructions = 0; supercycles = 0; loadcycles = 0; storecycles = 0; memset(reg, 0, sizeof(reg)); memset(iqueue, 0, sizeof(iqueue)); memset(icomplet, 0, sizeof(icomplet)); /* Cpu configuration */ mtspr(SPR_UPR, config.cpu.upr); setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver); setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev); mtspr(SPR_SR, config.cpu.sr); pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */ printf ("Starting at 0x%08x\n", pcnext); pc = pcnext; pc_phy = pc; pcnext += 4; debug(1, "reset ...\n"); /* MM1409: All programs should set their stack pointer! */ except_handle(EXCEPT_RESET, 0); } inline int cpu_clock () { if(fetch()) { printf ("Breakpoint hit.\n"); cont_run = 0; /* memory breakpoint encountered */ return 1; } decode_execute(&iqueue[0]); update_pc(); analysis(); if (config.sim.exe_log) dump_exe_log(); return 0; } /****************************************** * Instruction specific functions. * ******************************************/ void l_add() { signed long temp1; signed char temp4; IFF (config.cpu.dependstats) cur->func_unit = it_arith; temp1 = (signed long)eval_operand32(2, &breakpoint)+(signed long)eval_operand32(1, &breakpoint); set_operand32(0, temp1, &breakpoint); temp4 = temp1; if (temp4 == temp1) mstats.byteadd++; } void l_sw() { IFF (config.cpu.dependstats) cur->func_unit = it_store; set_operand32(0, eval_operand32(1, &breakpoint), &breakpoint); } void l_sb() { IFF (config.cpu.dependstats) cur->func_unit = it_store; set_operand8(0, eval_operand32(1, &breakpoint), &breakpoint); } void l_sh() { IFF (config.cpu.dependstats) cur->func_unit = it_store; set_operand16(0, eval_operand32(1, &breakpoint), &breakpoint); } void l_lwz() { unsigned long val; IFF (config.cpu.dependstats) cur->func_unit = it_load; val = eval_operand32(1, &breakpoint); /* If eval opreand produced exception don't set anything */ if (!pending.valid) set_operand32(0, val, &breakpoint); } void l_lbs() { signed char val; IFF (config.cpu.dependstats) cur->func_unit = it_load; val = eval_operand8(1, &breakpoint); /* If eval opreand produced exception don't set anything */ if (!pending.valid) set_operand32(0, val, &breakpoint); } void l_lbz() { unsigned char val; IFF (config.cpu.dependstats) cur->func_unit = it_load; val = eval_operand8(1, &breakpoint); /* If eval opreand produced exception don't set anything */ if (!pending.valid) set_operand32(0, val, &breakpoint); } void l_lhs() { signed short val; IFF (config.cpu.dependstats) cur->func_unit = it_load; val = eval_operand16(1, &breakpoint); /* If eval opreand produced exception don't set anything */ if (!pending.valid) set_operand32(0, val, &breakpoint); } void l_lhz() { unsigned short val; IFF (config.cpu.dependstats) cur->func_unit = it_load; val = eval_operand16(1, &breakpoint); /* If eval opreand produced exception don't set anything */ if (!pending.valid) set_operand32(0, val, &breakpoint); } void l_movhi() { IFF (config.cpu.dependstats) cur->func_unit = it_movimm; set_operand32(0, eval_operand32(1, &breakpoint) << 16, &breakpoint); } void l_and() { IFF (config.cpu.dependstats) cur->func_unit = it_arith; set_operand32(0, eval_operand32(1, &breakpoint) & (unsigned)eval_operand32(2, &breakpoint), &breakpoint); } void l_or() { IFF (config.cpu.dependstats) cur->func_unit = it_arith; set_operand32(0, eval_operand32(1, &breakpoint) | (unsigned)eval_operand32(2, &breakpoint), &breakpoint); } void l_xor() { IFF (config.cpu.dependstats) cur->func_unit = it_arith; set_operand32(0, eval_operand32(1, &breakpoint) ^ (signed)eval_operand32(2, &breakpoint), &breakpoint); } void l_sub() { IFF (config.cpu.dependstats) cur->func_unit = it_arith; set_operand32(0, (signed long)eval_operand32(1, &breakpoint) - (signed long)eval_operand32(2, &breakpoint), &breakpoint); } /*int mcount = 0;*/ void l_mul() { signed long temp3, temp2, temp1; IFF (config.cpu.dependstats) cur->func_unit = it_arith; set_operand32(0, (signed long)eval_operand32(1, &breakpoint) * (signed long)eval_operand32(2, &breakpoint), &breakpoint); /*if (!(mcount++ & 1023)) { printf ("[%i]\n",mcount); }*/ } void l_div() { signed long temp3, temp2, temp1; IFF (config.cpu.dependstats) cur->func_unit = it_arith; temp3 = eval_operand32(2, &breakpoint); temp2 = eval_operand32(1, &breakpoint); if (temp3) temp1 = temp2 / temp3; else { except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr); return; } set_operand32(0, temp1, &breakpoint); } void l_divu() { unsigned long temp3, temp2, temp1; IFF (config.cpu.dependstats) cur->func_unit = it_arith; temp3 = eval_operand32(2, &breakpoint); temp2 = eval_operand32(1, &breakpoint); temp1 = temp2 / temp3; /* cycles += 16; */ set_operand32(0, temp1, &breakpoint); } void l_sll() { int sign = 1; IFF (config.cpu.dependstats) cur->func_unit = it_shift; if ((signed)eval_operand32(1, &breakpoint) < 0) sign = -1; /* cycles += 2; */ set_operand32(0, eval_operand32(1, &breakpoint) << eval_operand32(2, &breakpoint), &breakpoint); } void l_sra() { unsigned long sign = 0; IFF (config.cpu.dependstats) cur->func_unit = it_shift; if ((signed)eval_operand32(1, &breakpoint) < 0) sign = -1; /* cycles += 2; */ set_operand32(0, (signed)eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint), &breakpoint); } void l_srl() { IFF (config.cpu.dependstats) cur->func_unit = it_shift; /* cycles += 2; */ set_operand32(0, eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint), &breakpoint); } void l_bf() { if (config.bpb.enabled) { int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0; IFF (config.cpu.dependstats) cur->func_unit = it_branch; mstats.bf[flag][fwd]++; bpb_update(cur->insn_addr, flag); } if (flag) { debug(5, "\nl.bf relative: pc=%x pcnext=%x\n", pc, pcnext); pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4; btic_update(pcnext); next_delay_insn = 1; } else { btic_update(pc); } } void l_bnf() { if (config.bpb.enabled) { int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0; IFF (config.cpu.dependstats) cur->func_unit = it_branch; mstats.bnf[!flag][fwd]++; bpb_update(cur->insn_addr, flag == 0); } if (flag == 0) { debug(5, "\nl.bnf relative: pc=%x pcnext=%x\n", pc, pcnext); pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4; btic_update(pcnext); next_delay_insn = 1; } else { btic_update(pc); } } void l_j() { debug(5, "\nl.j relative: pc=%x pcnext=%x\n", pc, pcnext); pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4; IFF (config.cpu.dependstats) cur->func_unit = it_jump; next_delay_insn = 1; } void l_jal() { debug(5, "\nl.jal relative: pc=%x pcnext=%x\n", pc, pcnext); pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4; IFF (config.cpu.dependstats) cur->func_unit = it_jump; set_reg32(LINK_REGNO, pc + 8); next_delay_insn = 1; if (config.sim.profile) { struct mem_entry *entry; struct label_entry *tmp; if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay))) fprintf (runtime.sim.fprof, "+%08X %08X %08X %s\n", cycles, pc + 8, pcdelay, tmp->name); else fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", cycles, pc + 8, pcdelay, pcdelay); } } void l_jalr() { IFF (config.cpu.dependstats) cur->func_unit = it_jump; pcdelay = eval_operand32(0, &breakpoint); set_reg32(LINK_REGNO, pc + 8); next_delay_insn = 1; } void l_jr() { IFF (config.cpu.dependstats) cur->func_unit = it_jump; pcdelay = eval_operand32(0, &breakpoint); next_delay_insn = 1; if (config.sim.profile) fprintf (runtime.sim.fprof, "-%08X %08X\n", cycles, pcdelay); } void l_rfe() { IFF (config.cpu.dependstats) cur->func_unit = it_exception; pcnext = mfspr(SPR_EPCR_BASE); mtspr(SPR_SR, mfspr(SPR_ESR_BASE)); } void l_nop() { unsigned long stackaddr; int k = eval_operand32(0, &breakpoint); IFF (config.cpu.dependstats) cur->func_unit = it_nop; switch (k) { case NOP_NOP: break; case NOP_EXIT: printf("exit(%d)\n", evalsim_reg32 (3)); if (config.debug.gdb_enabled) set_stall_state (1); else cont_run = 0; break; case NOP_PRINTF: stackaddr = evalsim_reg32(4); simprintf(stackaddr, evalsim_reg32(3)); debug(5, "simprintf %x\n", stackaddr); break; case NOP_REPORT: printf("report(0x%x);\n", evalsim_reg32(3)); default: if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST) printf("report %i (0x%x);\n", k - NOP_REPORT_FIRST, evalsim_reg(3)); break; } } void l_sfeq() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = eval_operand32(0, &breakpoint) == eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfne() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = eval_operand32(0, &breakpoint) != eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfgts() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (signed)eval_operand32(0, &breakpoint) > (signed)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfges() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (signed)eval_operand32(0, &breakpoint) >= (signed)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sflts() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (signed)eval_operand32(0, &breakpoint) < (signed)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfles() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (signed)eval_operand32(0, &breakpoint) <= (signed)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfgtu() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (unsigned)eval_operand32(0, &breakpoint) > (unsigned)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfgeu() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (unsigned)eval_operand32(0, &breakpoint) >= (unsigned) eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfltu() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (unsigned)eval_operand32(0, &breakpoint) < (unsigned)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_sfleu() { IFF (config.cpu.dependstats) cur->func_unit = it_compare; flag = (unsigned)eval_operand32(0, &breakpoint) <= (unsigned)eval_operand32(1, &breakpoint); setsprbits(SPR_SR, SPR_SR_F, flag); } void l_mtspr() { IFF (config.cpu.dependstats) cur->func_unit = it_move; if (mfspr(SPR_SR) & SPR_SR_SM) mtspr(eval_operand32(0, &breakpoint) + eval_operand32(2, &breakpoint), eval_operand32(1, &breakpoint)); else { printf("WARNING: trying to write SPR while SR[SUPV] is cleared.\n"); cont_run = 0; } } void l_mfspr() { IFF (config.cpu.dependstats) cur->func_unit = it_move; if (mfspr(SPR_SR) & SPR_SR_SM) set_operand32(0, mfspr(eval_operand32(1, &breakpoint) + eval_operand32(2, &breakpoint)), &breakpoint); else { set_operand32(0, 0, &breakpoint); printf("WARNING: trying to read SPR while SR[SUPV] is cleared.\n"); cont_run = 0; } } void l_sys() { except_handle(EXCEPT_SYSCALL, 0); } void l_trap() { /* TODO: some SR related code here! */ except_handle(EXCEPT_TRAP, 0); } void l_mac() { sprword lo, hi; LONGEST l; LONGEST x, y; IFF (config.cpu.dependstats) cur->func_unit = it_mac; lo = mfspr (SPR_MACLO); hi = mfspr (SPR_MACHI); x = eval_operand32(0, &breakpoint); y = eval_operand32(1, &breakpoint); printf ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y)); l = (ULONGEST)lo | ((LONGEST)hi << 32); l += (LONGEST) x * (LONGEST) y; /* This implementation is very fast - it needs only one cycle for mac. */ lo = ((ULONGEST)l) & 0xFFFFFFFF; hi = ((LONGEST)l) >> 32; mtspr (SPR_MACLO, lo); mtspr (SPR_MACHI, hi); printf ("(%08x,%08x)\n", hi, lo); } void l_msb() { sprword lo, hi; LONGEST l; IFF (config.cpu.dependstats) cur->func_unit = it_mac; lo = mfspr (SPR_MACLO); hi = mfspr (SPR_MACHI); l = (ULONGEST)lo | ((LONGEST)hi << 32); l -= (LONGEST) eval_operand32(0, &breakpoint) * (LONGEST)eval_operand32(1, &breakpoint); /* This implementation is very fast - it needs only one cycle for msb. */ lo = ((ULONGEST)l) & 0xFFFFFFFF; hi = ((LONGEST)l) >> 32; mtspr (SPR_MACLO, lo); mtspr (SPR_MACHI, hi); } void l_macrc() { sprword lo, hi; LONGEST l; /* No need for synchronization here -- all MAC instructions are 1 cycle long. */ lo = mfspr (SPR_MACLO); hi = mfspr (SPR_MACHI); l = (ULONGEST) lo | ((LONGEST)hi << 32); l >>= 28; //printf ("<%08x>\n", (unsigned long)l); set_operand32(0, (long)l, &breakpoint); mtspr (SPR_MACLO, 0); mtspr (SPR_MACHI, 0); } void l_cust1() { /*int destr = cur->insn >> 21; int src1r = cur->insn >> 15; int src2r = cur->insn >> 9;*/ } void l_cust2() { } void l_cust3() { } void l_cust4() { } void l_invalid() { except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr); }
Go to most recent revision | Compare with Previous | Blame | View Log