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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/types.h>  /* CZ 250801 */
#include <sys/stat.h>   /* CZ 250801 */
#include <fcntl.h>      /* CZ 250801 */ 
#include <sys/poll.h>   /* CZ 250801 */
#include <sys/time.h>   /* CZ 250801 */ 
#include <unistd.h>     /* CZ 250801 */ 
#include <errno.h>      /* CZ 250801 */ 
 
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
 
static struct dev_16450 uarts[NR_UARTS];
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static void set_char_clks(int uartchip)
{
	int bauds_per_char = 0;
 
	uarts[uartchip].char_clks = (uarts[uartchip].regs.dlh << 8)
					+ uarts[uartchip].regs.dll;
 
	if (uarts[uartchip].regs.lcr & UART_LCR_PARITY)
		bauds_per_char++;
 
	if (uarts[uartchip].regs.lcr & UART_LCR_STOP)
		bauds_per_char += 2;
	else
		bauds_per_char++;
 
	bauds_per_char += (5 + (uarts[uartchip].regs.lcr & 0x2));
 
	uarts[uartchip].char_clks *= bauds_per_char;
}
 
/* CZ 260801 --- The simulator expects to access only 32
   bit words. Since we only have an 8 bit data space, simply
   ignore the bottom 24 bits. */
/* Set a specific UART register with value. */
void uart_write(unsigned long addr, unsigned int arg_value)
{
	int chipsel;
	unsigned char value = arg_value >> 24;
 
	debug("uart_write(%x,%x)\n", addr, value);
 
	for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
		if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
			break;
		else if (chipsel == NR_UARTS)
			return;
 
	if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) 
	  {
	    switch (addr % UART_ADDR_SPACE)
	      {
	      case UART_DLL:
		uarts[chipsel].regs.dll = value;
		set_char_clks(chipsel);
		return;
	      case UART_DLH:
		uarts[chipsel].regs.dlh = value;
		set_char_clks(chipsel);
		return;
	      default: /* Fall through to normal processing */
		break;
	      }
	  }
 
	switch (addr % UART_ADDR_SPACE) {
		case UART_TXBUF:
			uarts[chipsel].regs.txbuf = value;
			uarts[chipsel].istat.txbuf = FULL;
			uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
			uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
			break;
		case UART_IER:
			uarts[chipsel].regs.ier = value & UART_VALID_IER;
			break;
		case UART_LCR:
			uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
			break;
		case UART_MCR:
			uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
			break;
		case UART_SCR:
			uarts[chipsel].regs.scr = value;
			break;
		default:
			debug("write out of range (addr %x)\n", addr);
	}
	set_char_clks(chipsel);
	return;
}
 
/* CZ 260801 --- The simulator expects to access only 32
   bit words. Since we only have an 8 bit data space, simply
   fill in the bottom 24 bits with zero */
/* Read a specific UART register. */
unsigned int uart_read(unsigned long addr)
{
	unsigned char value = 0;
	int chipsel;
 
	debug("uart_read(%x)\n", addr);
 
	for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
		if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
			break;
		else if (chipsel == NR_UARTS)
			return 0;
 
	if (uarts[chipsel].regs.lcr & UART_LCR_DLAB)
	  {
	    switch (addr % UART_ADDR_SPACE)
	      {
	      case UART_DLL:
		return uarts[chipsel].regs.dll << 24;
	      case UART_DLH:
		return uarts[chipsel].regs.dlh << 24;
	      default: /* Fall through to normal processing */
		break;
	      }
	  }
 
	switch (addr % UART_ADDR_SPACE) {
		case UART_RXBUF:
			value = uarts[chipsel].regs.rxbuf;
			uarts[chipsel].istat.rxbuf = EMPTY;
			uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
			break;
		case UART_IER:
			value = uarts[chipsel].regs.ier & UART_VALID_IER;
			break;
		case UART_IIR:
			value = uarts[chipsel].regs.iir & UART_VALID_IIR;
			break;
		case UART_LCR:
			value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
			break;
		case UART_MCR:
			value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
			break;
		case UART_LSR:
			value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
			uarts[chipsel].regs.lsr &=
				~(UART_LSR_OVRRUN | UART_LSR_PARITY
				 | UART_LSR_FRAME | UART_LSR_BREAK);
			break;
		case UART_MSR:
			value = uarts[chipsel].regs.msr & UART_VALID_MSR;
			uarts[chipsel].regs.msr = 0;
			break;
		case UART_SCR:
			value = uarts[chipsel].regs.scr;
			break;
		default:
			debug("read out of range (addr %x)\n", addr);
	}
	return value << 24;
}
 
 
/* Reset. It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space. */
void uart_reset()
{
  int i;
  static int initialized = 0; /* If we're not initialized, don't close it */
  int saved_tx_fds[NR_UARTS];
  int saved_rx_fds[NR_UARTS];
 
  if(initialized)
    {
      for(i = 0; i < NR_UARTS; i++)
	{
	  struct stat buf;
 
	  if(uarts[i].txfd >= 0)
	    {
	      if(fstat(uarts[i].txfd,&buf) ||
		 (!S_ISFIFO(buf.st_mode) &&
		  !S_ISSOCK(buf.st_mode)))
		{
		  close(uarts[i].txfd);
		  saved_tx_fds[i] = -1;
		}
	      else
		saved_tx_fds[i] = uarts[i].txfd;
	    }
	  else
	    saved_tx_fds[i] = -1;
 
	  if(uarts[i].rxfd >= 0)
	    {
	      if(fstat(uarts[i].rxfd,&buf) ||
		 (!S_ISFIFO(buf.st_mode) &&
		  !S_ISSOCK(buf.st_mode)))
		{
		  close(uarts[i].rxfd);
		  saved_rx_fds[i] = -1;
		}
	      else
		saved_rx_fds[i] = uarts[i].txfd;
	    }
	  else
	    saved_rx_fds[i] = -1;
	}
    }
  else
    {
      for(i=0;i<NR_UARTS;i++)
	saved_tx_fds[i] = saved_rx_fds[i] = -1;
      initialized = 1;
    }
 
  printf("Resetting %u UART(s).\n", NR_UARTS);
  memset(uarts, 0, sizeof(uarts));
  for(i=0;i<NR_UARTS;i++)
    {
      uarts[i].txfd = saved_tx_fds[i];
      uarts[i].rxfd = saved_rx_fds[i];
    }
 
  for(i = 0; i < NR_UARTS; i++)
    if (config.uarts[i].txfile) { /* MM: Try to create stream.  */
      /* CZ changed this to use descriptors and non blocking I/O */
      if ((uarts[i].rxfd = open(config.uarts[i].rxfile,
				O_RDONLY | O_NONBLOCK)) < 0)
	{
	  char sTemp[256];
 
	  sprintf(sTemp,"UART%d RX - \"%s\"",i,config.uarts[i].rxfile);
	  perror(sTemp);
	  continue;
	}
      if((uarts[i].txfd = open(config.uarts[i].txfile,
				O_WRONLY | O_NONBLOCK)) < 0)
	{
	  char sTemp[256];
 
	  if(errno == ENXIO)
	    {
	      /* In this case, we're a pipe, and the user has
		 forgotten to start the read process first. Help
		 him out by writing an error message and exiting */
 
	      fprintf(stderr,"Please start the serial port reader "
		      "before starting the simulator.\nIf you wish "
		      "to continue without this, please remove the "
		      "file \"%s\" and restart.\n",config.uarts[i].txfile);
	      fflush(stderr);
	      exit(1);
	    }
	  sprintf(sTemp,"UART%d TX - \"%s\"",i,config.uarts[i].txfile);
	  perror(sTemp);
	  close(uarts[i].rxfd);
	  uarts[i].rxfd = -1;
	  continue;
	}
      uarts[i].baseaddr = config.uarts[i].baseaddr;
      printf("UART%d at 0x%.8x uses ", i, uarts[i].baseaddr);
      printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile,
	     config.uarts[i].txfile);
      register_memoryarea(uarts[i].baseaddr, UART_ADDR_SPACE, 
			  uart_read, uart_write);
    }
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock()
{
	int i;
 
	for(i = 0; i < NR_UARTS; i++) {
 
	  if(uarts[i].txfd < 0)
	    continue;
 
	  /* Transmit */
	  if (uarts[i].istat.txser == EMPTY)
	    {
	      uarts[i].regs.lsr |= UART_LSR_TXBUFE;
	      if (uarts[i].istat.txbuf == FULL) 
		{
		  uarts[i].iregs.txser = uarts[i].regs.txbuf;
		  uarts[i].istat.txser = FULL;
		  uarts[i].istat.txbuf = EMPTY;
		  uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
		} 
	      else
		uarts[i].regs.lsr |= UART_LSR_TXSERE;
	    }
	  else if (uarts[i].char_clks == uarts[i].istat.txser_clks++)
	    {
	      debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
	      if (uarts[i].regs.mcr & UART_MCR_LOOP)
		uarts[i].iregs.loopback = uarts[i].iregs.txser;
	      else 
		switch(send_byte(uarts[i].txfd,config.uarts[i].jitter,
			       i,(int)uarts[i].iregs.txser))
		  {
		  case -1: /* An error occurred */
		    close(uarts[i].txfd);
		    close(uarts[i].rxfd);
		    uarts[i].txfd = uarts[i].rxfd = -1;
		    continue;
		  case 0:  /* The device wasn't ready */
		    uarts[i].istat.txser_clks = 0; /* Try again later */
		    break;
		  case 1:  /* OK...it got sent */
		    uarts[i].istat.txser = EMPTY;
		    uarts[i].istat.txser_clks = 0;
		    break;
		  }
	    }
 
	  /* Receive */
	  if (uarts[i].istat.rxser == EMPTY)
	    uarts[i].istat.rxser = FULL;
	  else if (uarts[i].char_clks == uarts[i].istat.rxser_clks++)
	    {
	      debug("Receiving via UART%d...\n", i);
	      if (uarts[i].regs.mcr & UART_MCR_LOOP)
		uarts[i].iregs.rxser = uarts[i].iregs.loopback;
	      else
		switch(receive_byte(uarts[i].rxfd,config.uarts[i].jitter,
				    i,&uarts[i].iregs.rxser))
		  {
		  case -1: /* An error occurred */
		    close(uarts[i].txfd);
		    close(uarts[i].rxfd);
		    uarts[i].txfd = uarts[i].rxfd = -1;
		    continue;
		  case 0:
		    uarts[i].istat.rxser_clks = 0;
		    break;
		  case 1:
		    uarts[i].istat.rxser = EMPTY;
		    uarts[i].istat.rxser_clks = 0;
		    if (uarts[i].istat.rxbuf == FULL)
		      uarts[i].regs.lsr |= UART_LSR_OVRRUN;
		    uarts[i].regs.lsr |= UART_LSR_RDRDY;
		    uarts[i].regs.rxbuf = uarts[i].iregs.rxser;
		    uarts[i].istat.rxbuf = FULL;
		    break;
		  }
	    }
 
	  /* Loopback */
	  if (uarts[i].regs.mcr & UART_MCR_LOOP) 
	    {
	      debug("uart_clock: Loopback\n");
	      if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
		  ((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
		uarts[i].regs.msr |= UART_MSR_DDCD;
	      if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
		  ((uarts[i].regs.msr & UART_MSR_RI) >> 4))
		uarts[i].regs.msr |= UART_MSR_TERI;
	      if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
		  ((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
		uarts[i].regs.msr |= UART_MSR_DCTS;
	      if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
		  ((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
		uarts[i].regs.msr |= UART_MSR_DDSR;
	      uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
				     | UART_MSR_DSR | UART_MSR_CTS);
	      uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
	      uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
	      uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
	      uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
	    }
 
	  /* Interrupt detection in proper priority order. */
	  uarts[i].regs.iir = UART_IIR_NO_INT;
	  if (uarts[i].regs.ier & UART_IER_RLSI &&
	      uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
				   | UART_LSR_FRAME | UART_LSR_BREAK))
	    {
	      uarts[i].regs.iir = UART_IIR_RLSI;
	    }
	  else if (uarts[i].regs.ier & UART_IER_RDI &&
		   uarts[i].regs.lsr & UART_LSR_RDRDY)
	    {
	      uarts[i].regs.iir = UART_IIR_RDI;
	    }
	  else if (uarts[i].regs.ier & UART_IER_THRI &&
		   uarts[i].regs.lsr & UART_LSR_TXBUFE)
	    {
	      uarts[i].regs.iir = UART_IIR_THRI;
	    }
	  else if (uarts[i].regs.ier & UART_IER_MSI &&
		   uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
					| UART_MSR_TERI | UART_MSR_DDCD))
	    {
	      uarts[i].regs.iir = UART_IIR_MSI;
	    }
	  if (!(uarts[i].regs.iir & UART_IIR_NO_INT))
	    report_interrupt(INT_UART);
	}
}
 
/* Print register values on stdout. */
void uart_status()
{
  int i;
 
  for(i = 0; i < NR_UARTS; i++) {
    if (uarts[i].txfd < 0)
      continue;
 
    printf("\nUART%d visible registers at 0x%.8x:\n", i, uarts[i].baseaddr);
    printf("RXBUF: %.2x  TXBUF: %.2x\n", uarts[i].regs.rxbuf, uarts[i].regs.txbuf);
    printf("DLL  : %.2x  DLH  : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
    printf("IER  : %.2x  IIR  : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
    printf("LCR  : %.2x  MCR  : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
    printf("LSR  : %.2x  MSR  : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
    printf("SCR  : %.2x\n", uarts[i].regs.scr);
 
    printf("\nInternal registers (sim debug):\n");
    printf("RXSER: %.2x  TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
 
    printf("\nInternal status (sim debug):\n");
    printf("char_clks: %d\n", uarts[i].char_clks);
    printf("rxser_clks: %d  txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
    printf("rxser: %d  txser: %d\n", uarts[i].istat.rxser, uarts[i].istat.txser);
    printf("rxbuf: %d  txbuf: %d\n", uarts[i].istat.rxbuf, uarts[i].istat.txbuf);
 
    printf("RX fd: %d  TX fd: %d\n\n", uarts[i].rxfd, uarts[i].txfd);
  }
}
 
/* Send a byte. Return 1 for OK. 0 for timeout. -1 if a
   system error occurred. Asynchronous port is implied by
   passing a negative number to the timeout field. In this
   case, the function will return without generating an
   error message if it can not send. This simulates
   congestion control from the external source. */
int send_byte(int fd,int timeout,int uart_id,int byte)
{
  struct timeval now;
  struct timeval until;
  struct pollfd set;
  int msecs = 0;
  unsigned char ch = byte;
 
  if(gettimeofday(&now,NULL) < 0)
    {
      now.tv_sec = time(NULL);
      now.tv_usec = 0;
    }
 
  until.tv_sec = now.tv_sec;
  if(timeout > 0)
    until.tv_usec = now.tv_usec + timeout*1000;
  else
    until.tv_usec = now.tv_usec;
 
  if(until.tv_usec > 999999)
    {
      until.tv_sec++;
      until.tv_usec -= 1000000;
    }
 
  msecs = timeout > 0 ? timeout : 0;
  set.fd = fd;
  set.events = POLLOUT;
  set.revents = 0;
 
  while(msecs >= 0)
    {
      char sTemp[256];
 
      switch(poll(&set,1,msecs))
	{
	case 1: /* We're good, or we got an error */
	  switch(write(fd,&ch,1))
	    {
	    case -1:
	      sprintf(sTemp,"UART %d TX - write",uart_id);
	      perror(sTemp);
	      fflush(stderr);
	      return -1;
	    case 0: 
	      fprintf(stderr,"UART %d TX EOF detected. Shutting down"
		      " to prevent endless loop.\n",uart_id);
	      fflush(stderr);
	      if(uarts[uart_id].txfd >= 0)
		close(uarts[uart_id].txfd);
	      if(uarts[uart_id].rxfd >= 0)
		close(uarts[uart_id].rxfd);
	      uarts[uart_id].txfd = uarts[uart_id].rxfd = -1;
	      return 0;
	    case 1:
	      return 1;
	    }
	case 0: /* We timed out. Stop the loop. */
	  msecs = -1;
	  break;
	case -1:
	  if(errno == EINTR)
	    {
	      if(gettimeofday(&now,NULL) < 0)
		{
		  now.tv_sec = time(NULL);
		  now.tv_usec = 0;
		}
	      msecs = (until.tv_sec - now.tv_sec)*1000 +
		until.tv_usec - now.tv_usec;
	      continue;
	    }
	  else
	    {
	      char sTemp[256];
 
	      sprintf(sTemp,"UART %d TX - poll",uart_id);
	      perror(sTemp);
	      fflush(stderr);
	      return -1;
	    }
	}
    }
 
  if(timeout >= 0)
    {
      fprintf(stderr,"Transmit timeout occurred on UART %d. Data "
	      "may be corrupt.\n",uart_id);
      fflush(stderr);
    }
  return 0;
}
 
/* Receive a byte. Return 1 for OK. 0 for timeout. -1 if a
   system error occurred. Asynchronous port is implied by
   passing a negative number to the timeout field. In this
   case, the function will return without generating an
   error message. */
int receive_byte(int fd,int timeout,int uart_id,unsigned char* byte)
{
  struct timeval now;
  struct timeval until;
  struct pollfd set;
  int msecs = 0;
 
  if(gettimeofday(&now,NULL) < 0)
    {
      now.tv_sec = time(NULL);
      now.tv_usec = 0;
    }
 
  until.tv_sec = now.tv_sec;
  if(timeout > 0)
    until.tv_usec = now.tv_usec + timeout*1000;
  else
    until.tv_usec = now.tv_usec;
 
  if(until.tv_usec > 999999)
    {
      until.tv_sec++;
      until.tv_usec -= 1000000;
    }
 
  msecs = timeout > 0 ? timeout : 0;
  set.fd = fd;
  set.events = POLLIN;
  set.revents = 0;
 
  while(msecs >= 0)
    {
      char sTemp[256];
 
      switch(poll(&set,1,msecs))
	{
	case 1: /* We're good, or we got an error */
	  switch(read(fd,byte,1))
	    {
	    case -1:
	      sprintf(sTemp,"UART %d RX - read",uart_id);
	      perror(sTemp);
	      fflush(stderr);
	      return -1;
	    case 0: 
	      fprintf(stderr,"UART %d RX EOF detected. Shutting down"
		      " to prevent endless loop.\n",uart_id);
	      fflush(stderr);
	      if(uarts[uart_id].txfd >= 0)
		close(uarts[uart_id].txfd);
	      if(uarts[uart_id].rxfd >= 0)
		close(uarts[uart_id].rxfd);
	      uarts[uart_id].txfd = uarts[uart_id].rxfd = -1;
	      return 0;
	    case 1:
	      return 1;
	    }
	case 0: /* We timed out. Stop the loop. */
	  *byte = 0xFF;
	  msecs = -1;
	  break;
	case -1:
	  if(errno == EINTR)
	    {
	      if(gettimeofday(&now,NULL) < 0)
		{
		  now.tv_sec = time(NULL);
		  now.tv_usec = 0;
		}
	      msecs = (until.tv_sec - now.tv_sec)*1000 +
		until.tv_usec - now.tv_usec;
	      continue;
	    }
	  else
	    {
	      char sTemp[256];
 
	      sprintf(sTemp,"UART %d RX - poll",uart_id);
	      perror(sTemp);
	      fflush(stderr);
	      return -1;
	    }
	}
    }
 
  if(timeout >= 0)
    {
      fprintf(stderr,"Receive timeout occurred on UART %d. Data "
	      "may be corrupt.\n",uart_id);
      fflush(stderr);
    }
  return 0;
}