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[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [cpu/] [or1k/] [except.c] - Rev 43

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/* except.c -- Simulation of OR1K exceptions
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "abstract.h"
#include "except.h"
#include "sprs.h"
 
extern int cont_run;
extern struct iqueue_entry iqueue[20];
extern unsigned long pc;
extern unsigned long pctemp;
 
/* Handle OR1K exceptions. */
void except_handle(int except, unsigned long ea)
{
	unsigned long pc_saved;
#if ONLY_VIRTUAL_MACHINE
	printf("WARNING: Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
	printf("Insn ADDR: 0x%x  Eff ADDR: 0x%x\n",  iqueue[0].insn_addr, ea);	
	printf("No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
#else
	if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
		printf("ABORT: Exception 0x%x (%s)", except, EXCEPT_NAME(except));
		printf(" occured while exception detection was disabled.\n");
		cont_run = 0;
		return;
	}
 
	printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
	printf("Insn ADDR: 0x%x  Eff ADDR: 0x%x\n",  iqueue[0].insn_addr, ea);
 
	pc_saved = (iqueue[0].insn_addr & ~0x1) | (mfspr(SPR_SR) & SPR_SR_SUPV);
	mtspr(SPR_EPCR_BASE, iqueue[0].insn_addr);
	mtspr(SPR_EEAR_BASE, ea);
	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);	/* SUPV mode */
	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);	/* Disable ints. */
	pc = (unsigned long)except;
	pctemp = (unsigned long)except;
#endif
}
 

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