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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [cache/] [icache_model.c] - Rev 26
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/* icache_model.c -- instruction cache simulation Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Cache functions. At the moment this functions only simulate functionality of instruction caches and do not influence on fetche/decode/execute stages and timings. They are here only to verify performance of various cache configurations. */ #include <stdio.h> #include <string.h> #include <errno.h> #include <stdarg.h> #include "icache_model.h" #include "abstract.h" #include "stats.h" /* Instruction cache */ /* Number of IC sets (power of 2) */ #define IC_SETS 128 /* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */ #define IC_BLOCK_SIZE 16 /* Number of IC ways (1, 2, 3 etc.). */ #define IC_WAYS 1 /* Number of usage states (2, 3, 4 etc.). */ #define IC_USTATES 2 struct ic_set { struct { unsigned long tagaddr; /* tag address */ int lru; /* least recently used */ } way[IC_WAYS]; } ic[IC_SETS]; void ic_info() { printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024); printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE); } /* First check if instruction is already in the cache and if it is: - increment IC read hit stats, - set 'lru' at this way to IC_USTATES - 1 and decrement 'lru' of other ways unless they have reached 0, and if not: - increment IC read miss stats - find lru way and entry and replace old tag with tag of the 'fetchaddr' - set 'lru' with IC_USTATES - 1 and decrement 'lru' of other ways unless they have reached 0 */ void ic_simulate(unsigned long fetchaddr) { int set, way = -1; int i; unsigned long tagaddr; /* Which set to check out? */ set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS; tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS; /* Scan all ways and try to find a matching way. */ for (i = 0; i < IC_WAYS; i++) if (ic[set].way[i].tagaddr == tagaddr) way = i; /* Did we find our cached instruction? */ if (way >= 0) { /* Yes, we did. */ ic_stats.readhit++; for (i = 0; i < IC_WAYS; i++) if (ic[set].way[i].lru) ic[set].way[i].lru--; ic[set].way[way].lru = IC_USTATES - 1; } else { /* No, we didn't. */ int minlru = IC_USTATES - 1; int minway = 0; ic_stats.readmiss++; for (i = 0; i < IC_WAYS; i++) if (ic[set].way[i].lru < minlru) minway = i; ic[set].way[minway].tagaddr = tagaddr; for (i = 0; i < IC_WAYS; i++) if (ic[set].way[i].lru) ic[set].way[i].lru--; ic[set].way[minway].lru = IC_USTATES - 1; } }
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