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/* config.h -- Simulator configuration header file
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#ifndef _CONFIG_H_
#define _CONFIG_H_
 
#include <stdio.h>
 
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
 
#define MAX_UARTS        4       /* Max. number of UARTs simulated */   
#define MAX_DMAS         4       /* Max. number of DMA controllers */
#define MAX_ETHERNETS    4       /* Max. number of Ethernet MACs   */
#define MAX_GPIOS        4       /* Max. number of GPIO modules    */
#define MAX_MEMORIES     16      /* Max. number of memory devices attached */
#define MAX_SBUF_LEN     256     /* Max. length of store buffer */
 
#define STR_SIZE        (256)
 
struct config {
  struct {
    int enabled;                      /* Is tick timer enabled?  */
  } tick;
 
  int nuarts;
  struct {
    char rxfile[STR_SIZE];            /* Filename for RX */
    char txfile[STR_SIZE];            /* Filename for TX (required) */
    int jitter;                       /* CZ 250801 - in msecs...time to block */
    unsigned long baseaddr;           /* Naturally aligned base address */
    int irq;                          /* IRQ of this device */
    unsigned long vapi_id;            /* VAPI id for this instance */
    int uart16550;                    /* Whether this device is uart 16450 or 16550 */
  } uarts[MAX_UARTS];
 
  int ndmas;
  struct {
    unsigned long baseaddr;
    int irq;                          /* IRQ of this device */
    unsigned long vapi_id;            /* VAPI id for this instance */
  } dmas[MAX_DMAS];
 
  int nethernets;
  struct {
    unsigned long baseaddr;
    unsigned dma;                     /* Which controller is this ethernet "connected" to */
    unsigned tx_channel;              /* DMA channel used for TX */
    unsigned rx_channel;              /* DMA channel used for RX */
    char rxfile[STR_SIZE];            /* Filename for RX */
    char txfile[STR_SIZE];            /* File for TX */
    unsigned long vapi_id;            /* VAPI id for this instance */
  } ethernets[MAX_ETHERNETS];
 
  int ngpios;
  struct {
    unsigned long baseaddr;           /* Base address */ 
    int irq;                          /* IRQ of this device */
    unsigned long base_vapi_id;       /* First VAPI ID.  GPIO uses 8 consecutive IDs */
  } gpios[MAX_GPIOS];
 
  struct {
    int enabled;                      /* is MC enabled? */
    unsigned long baseaddr;           /* Naturally aligned base address */
    unsigned POC;                     /* power on reset configuration register */
  } mc;
 
  struct {
    int pattern;                      /* A user specified memory initialization pattern */
    int random_seed;                  /* Initialize the memory with random values, starting with seed */
    enum {
      MT_UNKNOWN,
      MT_PATTERN,
      MT_RANDOM
    } type;
    int nmemories;                    /* Number of attached memories */
    struct {
      int ce;                         /* Which ce this memory is associated with */
      unsigned long baseaddr;         /* Start address of the memory */
      unsigned long size;             /* Memory size */
      char name[STR_SIZE];            /* Memory type string */
      char log[STR_SIZE];             /* Memory log filename */
      int delayr;                     /* Read cycles */
      int delayw;                     /* Write cycles */
    } table[MAX_MEMORIES];
  } memory;
 
  struct {
    int enabled;                      /* Whether IMMU is enabled */
    int nways;                        /* Number of ITLB ways */
    int nsets;                        /* Number of ITLB sets */
    int pagesize;                     /* ITLB page size */
    int entrysize;                    /* ITLB entry size */
    int ustates;                      /* number of ITLB usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } immu;
 
  struct {
    int enabled;                      /* Whether DMMU is enabled */
    int nways;                        /* Number of DTLB ways */
    int nsets;                        /* Number of DTLB sets */
    int pagesize;                     /* DTLB page size */
    int entrysize;                    /* DTLB entry size */
    int ustates;                      /* number of DTLB usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } dmmu;
 
  struct {
    int tagtype;
    int enabled;                      /* Whether instruction cache is enabled */
    int nways;                        /* Number of IC ways */
    int nsets;                        /* Number of IC sets */
    int blocksize;                    /* IC entry size */
    int ustates;                      /* number of IC usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } ic;
 
  struct {
    int enabled;                      /* Whether data cache is enabled */
    int tagtype;
    int nways;                        /* Number of DC ways */
    int nsets;                        /* Number of DC sets */
    int blocksize;                    /* DC entry size */
    int ustates;                      /* number of DC usage states */
    int store_missdelay;              /* How much cycles does the store miss cost */
    int store_hitdelay;               /* How much cycles does the store hit cost */
    int load_missdelay;               /* How much cycles does the load miss cost */
    int load_hitdelay;                /* How much cycles does the load hit cost */
  } dc;
 
  struct {
    int enabled;            /* branch prediction buffer analysis */
    int sbp_bnf_fwd;        /* Static branch prediction for l.bnf uses forward prediction */
    int sbp_bf_fwd;         /* Static branch prediction for l.bf uses forward prediction */    
    int btic;		    /* branch prediction target insn cache analysis */
    int missdelay;          /* How much cycles does the miss cost */
    int hitdelay;           /* How much cycles does the hit cost */
#if 0
    int nways;              /* Number of BP ways */
    int nsets;              /* Number of BP sets */
    int blocksize;          /* BP entry size */
    int ustates;            /* number of BP usage states */
    int pstates;            /* number of BP predict states */
#endif
  } bpb;
 
  struct {
    unsigned long upr;      /* Unit present register */
    unsigned long ver, rev; /* Version register */
    int sr;                 /* Supervision register */
    int superscalar;        /* superscalara analysis */
    int hazards;            /* dependency hazards analysis */
    int dependstats;        /* dependency statistics */
    int raw_range;          /* raw register usage over time stats; range in cycles, 0 = disabled */
    int sbuf_len;           /* length of store buffer, zero if disabled */
  } cpu;
 
  struct {
    int debug;              /* Simulator debugging */
    int verbose;            /* Force verbose output */
 
    int profile;            /* Is profiler running */
    char prof_fn[STR_SIZE]; /* Profiler filename */
 
    int mprofile;           /* Is memory profiler running */
    char mprof_fn[STR_SIZE];/* Memory profiler filename */
 
    int history;            /* instruction stream history analysis */
    int exe_log;            /* Print out RTL states? */
    char exe_log_fn[STR_SIZE]; /* RTL state comparison filename */
    int spr_log;            /* Print out SPR states */
    char spr_log_fn[STR_SIZE]; /* SPR state log filename */
    long clkcycle_ps;       /* Clock duration in ps */
  } sim;
 
  struct {
    int enabled;            /* Whether is debug module enabled */
    int gdb_enabled;        /* Whether is debugging with gdb possible */
    int server_port;        /* A user specified port number for services */
    unsigned long vapi_id;  /* "Fake" vapi device id for JTAG proxy */
  } debug;
 
  struct {                  /* Verification API, part of Advanced Core Verification */
    int enabled;            /* Whether is VAPI module enabled */
    int server_port;        /* A user specified port number for services */
    int log_enabled;        /* Whether to log the vapi requests */
    int hide_device_id;     /* Whether to log device ID for each request */
    char vapi_fn[STR_SIZE]; /* vapi log filename */
  } vapi;
 
  struct {
    int enabled;            /* Whether power menagement is operational */
  } pm;
};
 
struct runtime {
  struct {
    FILE *fprof;            /* Profiler file */
    FILE *fmprof;           /* Memory profiler file */
    FILE *fexe_log;         /* RTL state comparison file */
    FILE *fspr_log;         /* SPR state log file */
    int init;               /* Whether we are still initilizing sim */
    int script_file_specified;/* Whether script file was already loaded */
    char *filename;         /* Original Command Simulator file (CZ) */
    int output_cfg;         /* Whether sim is to output cfg files */
    char script_fn[STR_SIZE];/* Script file read */
    int iprompt;            /* Interactive prompt */
  } sim;
 
  struct {
    unsigned long ifea;     /* Instruction fetch effective address */
    unsigned long lea;      /* Load effective address */
    unsigned long sea;      /* Store effective address */
    unsigned long ld;       /* Load data */
    unsigned long sd;       /* Store data */
    unsigned long lsea;     /* Load/Store effective address */
  } cpu;
 
  struct {
    int random_seed;                  /* Initialize the memory with random values, starting with seed */
  } memory;
 
  struct {                  /* Verification API, part of Advanced Core Verification */
    int enabled;            /* Whether is VAPI module enabled */
    FILE *vapi_file;        /* vapi file */
    int server_port;        /* A user specified port number for services */
  } vapi;
};
 
#if FAST_SIM
#include "fast_config.c"
#define IFF(x) if (x)
#else
extern struct config config;
#define IFF(x) if (1)
#endif
 
extern struct runtime runtime;
 
/* Read environment from a script file. Does not fail - assumes defaukt configuration instead. */
void read_script_file (char *filename);
 
/* Executes set sim command.  Returns nonzero if error.  */
void set_config_command (char *s);
 
/* Outputs C structure of current config to file */
void output_cfg (FILE *f);
 
#endif