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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
 
static struct dev_16450 uarts[NR_UARTS];
static int thre_int;
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static void set_char_clks(int uartchip)
{
	int bauds_per_char = 0;
 
	uarts[uartchip].char_clks = (uarts[uartchip].regs.dlh << 8)
					+ uarts[uartchip].regs.dll;
 
	if (uarts[uartchip].regs.lcr & UART_LCR_PARITY)
		bauds_per_char++;
 
	if (uarts[uartchip].regs.lcr & UART_LCR_STOP)
		bauds_per_char += 2;
	else
		bauds_per_char++;
 
	bauds_per_char += (5 + (uarts[uartchip].regs.lcr & 0x2));
 
	uarts[uartchip].char_clks *= bauds_per_char;
}
 
/* Set a specific UART register with value. */
void uart_write_byte(unsigned long addr, unsigned long value)
{
	int chipsel;
 
	debug("uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
 
	for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
		if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
			break;
		else if (chipsel == NR_UARTS)
			return;
 
	if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
		switch (addr % UART_ADDR_SPACE) {
			case UART_DLL:
				uarts[chipsel].regs.dll = value;
				break;
			case UART_DLH:
				uarts[chipsel].regs.dlh = value;
				break;
			case UART_LCR:
				uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
				break;
			default:
				debug("write out of range (addr %x, DLAB=1)\n", addr);
		}
		set_char_clks(chipsel);
		return;
	}
 
	switch (addr % UART_ADDR_SPACE) {
		case UART_TXBUF:
			uarts[chipsel].regs.txbuf = value;
			uarts[chipsel].istat.txbuf = FULL;
			uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
			uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
			uarts[chipsel].istat.thre_int = 0;
			break;
		case UART_IER:
			uarts[chipsel].regs.ier = value & UART_VALID_IER;
			break;
		case UART_LCR:
			uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
			break;
		case UART_MCR:
			uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
			break;
		case UART_SCR:
			uarts[chipsel].regs.scr = value;
			break;
		default:
			debug("write out of range (addr %x)\n", addr);
	}
	set_char_clks(chipsel);
	return;
}
 
/* Read a specific UART register. */
unsigned long uart_read_byte(unsigned long addr)
{
	unsigned char value = 0;
	int chipsel;
 
	debug("uart_read_byte(%x)\n", addr);
 
	for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
		if ((addr & ~(UART_ADDR_SPACE-1)) == uarts[chipsel].baseaddr)
			break;
		else if (chipsel == NR_UARTS)
			return 0;
 
	if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
		switch (addr % UART_ADDR_SPACE) {
			case UART_DLL:
				value = uarts[chipsel].regs.dll;
				break;
			case UART_DLH:
				value = uarts[chipsel].regs.dlh;
				break;
			default:
				debug("read out of range (addr %x, DLAB=1)\n", addr);
		}
		return value;
	}
 
	switch (addr % UART_ADDR_SPACE) {
		case UART_RXBUF:
			value = uarts[chipsel].regs.rxbuf;
			uarts[chipsel].istat.rxbuf = EMPTY;
			uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
			break;
		case UART_IER:
			value = uarts[chipsel].regs.ier & UART_VALID_IER;
			break;
		case UART_IIR:
			value = uarts[chipsel].regs.iir & UART_VALID_IIR;
			uarts[chipsel].istat.thre_int = 0;
			break;
		case UART_LCR:
			value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
			break;
		case UART_MCR:
			value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
			break;
		case UART_LSR:
			value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
			uarts[chipsel].regs.lsr &=
				~(UART_LSR_OVRRUN | UART_LSR_PARITY
				 | UART_LSR_FRAME | UART_LSR_BREAK);
			break;
		case UART_MSR:
			value = uarts[chipsel].regs.msr & UART_VALID_MSR;
			uarts[chipsel].regs.msr = 0;
			break;
		case UART_SCR:
			value = uarts[chipsel].regs.scr;
			break;
		default:
			debug("read out of range (addr %x)\n", addr);
	}
	return value;
}
 
/* Reset. It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space. */
void uart_reset()
{
	int i;
 
	printf("Resetting %u UART(s).\n", NR_UARTS);
	memset(uarts, 0, sizeof(uarts));
 
	for(i = 0; i < NR_UARTS; i++)
		if (config.uarts[i].txfile) { /* MM: Try to create stream.  */
			if (!(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r"))
				&& !(uarts[i].rxfs = fopen(config.uarts[i].rxfile, "r+"))) {
				printf("UART%d has problems with RX file stream.\n", i);
				continue;
			}
			uarts[i].txfs = fopen(config.uarts[i].txfile, "a");
			uarts[i].baseaddr = config.uarts[i].baseaddr;
			if (uarts[i].rxfs && uarts[i].txfs) {
				printf("UART%d at 0x%.8x uses ", i, uarts[i].baseaddr);
				printf("%s for RX and %s for TX.\n", config.uarts[i].rxfile, config.uarts[i].txfile);
			} else
				printf("UART%d has problems with TX file stream.\n", i);
			register_memoryarea(uarts[i].baseaddr, UART_ADDR_SPACE, 1, uart_read_byte, uart_write_byte, 0);
		}
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock()
{
	int i, retval;
 
	for(i = 0; i < NR_UARTS; i++) {
		if (!uarts[i].txfs) {
			continue;
		}	
 
		/* Transmit */
		if (uarts[i].istat.txser == EMPTY) {
			uarts[i].regs.lsr |= UART_LSR_TXBUFE;
			if (uarts[i].istat.txbuf == FULL) {
				uarts[i].iregs.txser = uarts[i].regs.txbuf;
				uarts[i].istat.txser = FULL;
				uarts[i].istat.txbuf = EMPTY;
				uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
				uarts[i].istat.thre_int = 1;
			} else
				uarts[i].regs.lsr |= UART_LSR_TXSERE;
		} else if (uarts[i].char_clks == uarts[i].istat.txser_clks++) {
			debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
			if (uarts[i].regs.mcr & UART_MCR_LOOP)
				uarts[i].iregs.loopback = uarts[i].iregs.txser;
			else {
				fputc((int)uarts[i].iregs.txser, uarts[i].txfs);
				fflush(uarts[i].txfs);
			}
			uarts[i].istat.txser = EMPTY;
			uarts[i].istat.txser_clks = 0;
		}
 
		/* Receive */
		if (uarts[i].istat.rxser == EMPTY)
			uarts[i].istat.rxser = FULL;
		else if (uarts[i].char_clks == uarts[i].istat.rxser_clks++) {
			debug("Receiving via UART%d...\n", i);
			if (uarts[i].regs.mcr & UART_MCR_LOOP)
				uarts[i].iregs.rxser = uarts[i].iregs.loopback;
			else if((retval = fgetc(uarts[i].rxfs)) != EOF) {
				uarts[i].iregs.rxser = (char)retval;
				if (uarts[i].istat.rxbuf == FULL)
					uarts[i].regs.lsr |= UART_LSR_OVRRUN;
				uarts[i].regs.lsr |= UART_LSR_RDRDY;
				uarts[i].regs.rxbuf = uarts[i].iregs.rxser;
				uarts[i].istat.rxbuf = FULL;
			}
			uarts[i].istat.rxser = EMPTY;
			uarts[i].istat.rxser_clks = 0;
		}
 
		/* Loopback */
		if (uarts[i].regs.mcr & UART_MCR_LOOP) {
			debug("uart_clock: Loopback\n");
			if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
			    ((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
				uarts[i].regs.msr |= UART_MSR_DDCD;
			if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
			    ((uarts[i].regs.msr & UART_MSR_RI) >> 4))
				uarts[i].regs.msr |= UART_MSR_TERI;
			if ((uarts[i].regs.mcr & UART_MCR_RTS) !=
			    ((uarts[i].regs.msr & UART_MSR_CTS) >> 3))
				uarts[i].regs.msr |= UART_MSR_DCTS;
			if ((uarts[i].regs.mcr & UART_MCR_DTR) !=
			    ((uarts[i].regs.msr & UART_MSR_DSR) >> 5))
				uarts[i].regs.msr |= UART_MSR_DDSR;
			uarts[i].regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
					      | UART_MSR_DSR | UART_MSR_CTS);
			uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX2) << 4);
			uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
			uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
			uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
		}
 
		/* Interrupt detection in proper priority order. */
		uarts[i].regs.iir = UART_IIR_NO_INT;
		if (uarts[i].regs.ier & UART_IER_RLSI &&
		    uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
					| UART_LSR_FRAME | UART_LSR_BREAK)) {
			uarts[i].regs.iir = UART_IIR_RLSI;
		}
		else if (uarts[i].regs.ier & UART_IER_RDI &&
		    uarts[i].regs.lsr & UART_LSR_RDRDY) {
			uarts[i].regs.iir = UART_IIR_RDI;
		}
		else if (uarts[i].regs.ier & UART_IER_THRI &&
		    uarts[i].regs.lsr & UART_LSR_TXBUFE	&&
		    uarts[i].istat.thre_int == 1) {
			uarts[i].regs.iir = UART_IIR_THRI;
		}
		else if (uarts[i].regs.ier & UART_IER_MSI &&
		    uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
					| UART_MSR_TERI | UART_MSR_DDCD)) {
			uarts[i].regs.iir = UART_IIR_MSI;
		}
		if (!(uarts[i].regs.iir & UART_IIR_NO_INT))
			report_interrupt(INT_UART);
	}
}
 
/* Print register values on stdout. */
void uart_status()
{
	int i;
 
	for(i = 0; i < NR_UARTS; i++) {
		if ( !uarts[i].baseaddr )
			continue;
		printf("\nUART%d visible registers at 0x%.8x:\n", i, uarts[i].baseaddr);
		printf("RXBUF: %.2x  TXBUF: %.2x\n", uarts[i].regs.rxbuf, uarts[i].regs.txbuf);
		printf("DLL  : %.2x  DLH  : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
		printf("IER  : %.2x  IIR  : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
		printf("LCR  : %.2x  MCR  : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
		printf("LSR  : %.2x  MSR  : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
		printf("SCR  : %.2x\n", uarts[i].regs.scr);
 
		printf("\nInternal registers (sim debug):\n");
		printf("RXSER: %.2x  TXSER: %.2x\n", uarts[i].iregs.rxser, uarts[i].iregs.txser);
 
		printf("\nInternal status (sim debug):\n");
		printf("char_clks: %d\n", uarts[i].char_clks);
		printf("rxser_clks: %d  txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
		printf("rxser: %d  txser: %d\n", uarts[i].istat.rxser, uarts[i].istat.txser);
		printf("rxbuf: %d  txbuf: %d\n", uarts[i].istat.rxbuf, uarts[i].istat.txbuf);
 
		printf("RX fs: %p  TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
	}
}