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/* dcache_model.c -- data cache simulation
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator. 
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Cache functions. 
   At the moment this functions only simulate functionality of data
   caches and do not influence on fetche/decode/execute stages and timings.
   They are here only to verify performance of various cache configurations.
 */
 
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <stdarg.h>
 
#include "dcache_model.h"
#include "abstract.h"
#include "stats.h"
#include "spr_defs.h"
#include "sprs.h"
 
/* Data cache */
 
/* Number of DC sets (power of 2) */
#define DC_SETS 512
 
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
#define DC_BLOCK_SIZE 16
 
/* Number of DC ways (1, 2, 3 etc.). */
#define DC_WAYS 1
 
/* Number of usage states (2, 3, 4 etc.). */
#define DC_USTATES 2
 
struct dc_set {
	struct {
		unsigned long tagaddr;	/* tag address */
		int lru;		/* least recently used */
	} way[DC_WAYS];
} dc[DC_SETS];
 
void dc_info()
{
	if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
		printf("DCache not implemented. Set UPR[DCP].\n");
		return;
	}
 
	printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
	printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
}
 
/* First check if data is already in the cache and if it is:
    - increment DC read hit stats,
    - set 'lru' at this way to DC_USTATES - 1 and
      decrement 'lru' of other ways unless they have reached 0,
   and if not:
    - increment DC read miss stats
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
    - set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
void dc_simulate_read(unsigned long dataaddr)
{
	int set, way = -1;
	int i;
	unsigned long tagaddr;
 
	if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
		return;
 
	/* Which set to check out? */
	set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
	tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
 
	/* Scan all ways and try to find a matching way. */
	for (i = 0; i < DC_WAYS; i++)
		if (dc[set].way[i].tagaddr == tagaddr)
			way = i;
 
	/* Did we find our cached data? */
	if (way >= 0) { /* Yes, we did. */
		dc_stats.readhit++;
 
		for (i = 0; i < DC_WAYS; i++)
			if (dc[set].way[i].lru)
				dc[set].way[i].lru--;
		dc[set].way[way].lru = DC_USTATES - 1;
	}
	else {	/* No, we didn't. */
		int minlru = DC_USTATES - 1;
		int minway = 0;
 
                dc_stats.readmiss++;
 
		for (i = 0; i < DC_WAYS; i++)
			if ((dc[set].way[i].lru < minlru) && 
			    (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
				minway = i;
 
		dc[set].way[minway].tagaddr = tagaddr;
		for (i = 0; i < DC_WAYS; i++)
			if (dc[set].way[i].lru)
				dc[set].way[i].lru--;
		dc[set].way[minway].lru = DC_USTATES - 1;
	}
}
 
/* First check if data is already in the cache and if it is:
    - increment DC write hit stats,
    - set 'lru' at this way to DC_USTATES - 1 and
      decrement 'lru' of other ways unless they have reached 0,
   and if not:
    - increment DC write miss stats
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
    - set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
void dc_simulate_write(unsigned long dataaddr)
{
	int set, way = -1;
	int i;
	unsigned long tagaddr;
 
	if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
		return;
 
	/* Which set to check out? */
	set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
	tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
 
	/* Scan all ways and try to find a matching way. */
	for (i = 0; i < DC_WAYS; i++)
		if (dc[set].way[i].tagaddr == tagaddr)
			way = i;
 
	/* Did we find our cached data? */
	if (way >= 0) { /* Yes, we did. */
		dc_stats.writehit++;
 
		for (i = 0; i < DC_WAYS; i++)
			if (dc[set].way[i].lru)
				dc[set].way[i].lru--;
		dc[set].way[way].lru = DC_USTATES - 1;
	}
	else {	/* No, we didn't. */
		int minlru = DC_USTATES - 1;
		int minway = 0;
 
                dc_stats.writemiss++;
 
		for (i = 0; i < DC_WAYS; i++)
			if ((dc[set].way[i].lru < minlru) &&
			    (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
				minway = i;
 
		dc[set].way[minway].tagaddr = tagaddr;
		for (i = 0; i < DC_WAYS; i++)
			if (dc[set].way[i].lru)
				dc[set].way[i].lru--;
		dc[set].way[minway].lru = DC_USTATES - 1;
	}
}
 
/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
   otherwise don't do anything.
*/
 
void dc_inv(unsigned long dataaddr)
{
	int set, way = -1;
	int i;
	unsigned long tagaddr;
 
	if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
		return;
 
	/* Which set to check out? */
	set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
	tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
 
	/* Scan all ways and try to find a matching way. */
	for (i = 0; i < DC_WAYS; i++)
		if (dc[set].way[i].tagaddr == tagaddr)
			way = i;
 
	/* Did we find our cached data? */
	if ((way >= 0) && (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << way))) { /* Yes, we did. */
		dc[set].way[way].tagaddr = -1;
	}
}
 
void dc_clock()
{
	unsigned long addr;
 
	if (addr = mfspr(SPR_DCBPR)) {
		dc_simulate_read(addr);
		mtspr(SPR_DCBPR, 0);
	}
	if (addr = mfspr(SPR_DCBFR)) {
		dc_inv(addr);
		mtspr(SPR_DCBFR, 0);
	}
	if (addr = mfspr(SPR_DCBIR)) {
		dc_inv(addr);
		mtspr(SPR_DCBIR, 0);
	}
	if (addr = mfspr(SPR_DCBWR)) {
		mtspr(SPR_DCBWR, 0);
	}
	if (addr = mfspr(SPR_DCBLR)) {
		mtspr(SPR_DCBLR, 0);
	}
}