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[/] [or1k/] [tags/] [nog_patch_72/] [or1ksim/] [sim-config.h] - Rev 426
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/* config.h -- Simulator configuration header file Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <stdio.h> /* Simulator configuration macros. Eventually this one will be a lot bigger. */ #define MAX_UARTS 4 /* Max. number of UARTs simulated */ #define MAX_DMAS 4 /* Max. number of DMA controllers */ #define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */ #define MAX_MEMORIES 16 /* Max. number of memory devices attached */ #define NONE 0 #define VIRTUAL 1 #define PHYSICAL 2 #define STR_SIZE (256) struct config { struct { int tagtype; } dc; struct { int tagtype; } ic; struct { int enabled; /* Is tick timer enabled? */ int irq; /* IRQ of this device */ } tick; int clkcycle_ns; /* Clock cycle in nanoseconds */ int nuarts; int uarts_enabled; struct { char rxfile[STR_SIZE]; /* Filename for RX */ char txfile[STR_SIZE]; /* Filename for TX (required) */ int jitter; /* CZ 250801 - in msecs...time to block */ unsigned long baseaddr; /* Naturally aligned base address */ int irq; /* IRQ of this device */ unsigned long vapi_id; /* VAPI id for this instance */ int uart16550; /* Whether this device is uart 16450 or 16550 */ } uarts[MAX_UARTS]; int ndmas; int dmas_enabled; struct { unsigned long baseaddr; int irq; /* IRQ of this device */ unsigned long vapi_id; /* VAPI id for this instance */ } dmas[MAX_DMAS]; int nethernets; int ethernets_enabled; struct { unsigned long baseaddr; unsigned dma; /* Which controller is this ethernet "connected" to */ unsigned tx_channel; /* DMA channel used for TX */ unsigned rx_channel; /* DMA channel used for RX */ char rxfile[STR_SIZE]; /* Filename for RX */ char txfile[STR_SIZE]; /* File for TX */ unsigned long vapi_id; /* VAPI id for this instance */ } ethernets[MAX_ETHERNETS]; struct { int enabled; /* is MC enabled? */ unsigned long baseaddr; /* Naturally aligned base address */ unsigned POC; /* power on reset configuration register */ } mc; struct { int pattern; /* A user specified memory initialization pattern */ int random_seed; /* Initialize the memory with random values, starting with seed */ enum { MT_UNKNOWN, MT_PATTERN, MT_RANDOM } type; int nmemories; /* Number of attached memories */ struct { int ce; /* Which ce this memory is associated with */ unsigned long baseaddr; /* Start address of the memory */ unsigned long size; /* Memory size */ char name[STR_SIZE]; /* Memory type string */ char log[STR_SIZE]; /* Memory log filename */ int delayr; /* Read cycles */ int delayw; /* Write cycles */ } table[MAX_MEMORIES]; } memory; struct { int enabled; /* Whether IMMU is enabled */ int nways; /* Number of ITLB ways */ int nsets; /* Number of ITLB sets */ int pagesize; /* ITLB page size */ int entrysize; /* ITLB entry size */ int ustates; /* number of ITLB usage states */ } immu; struct { int enabled; /* Whether DMMU is enabled */ int nways; /* Number of DTLB ways */ int nsets; /* Number of DTLB sets */ int pagesize; /* DTLB page size */ int entrysize; /* DTLB entry size */ int ustates; /* number of DTLB usage states */ } dmmu; struct { unsigned long upr; /* Unit present register */ unsigned long ver, rev; /* Version register */ int superscalar; /* superscalara analysis */ int hazards; /* dependency hazards analysis */ int dependstats; /* dependency statistics */ int slp; /* subroutine level parallelism */ int btic; /* branch prediction target insn cache analysis */ int bpb; /* branch prediction buffer analysis */ } cpu; struct { int debug; /* Simulator debugging */ int verbose; /* Force verbose output */ int iprompt; /* Interactive prompt */ int profile; /* Is profiler running */ char prof_fn[STR_SIZE]; /* Profiler filename */ int history; /* instruction stream history analysis */ int exe_log; /* Print out RTL states? */ char exe_log_fn[STR_SIZE]; /* RTL state comparison filename */ } sim; struct { int enabled; /* Whether is debug module enabled */ int gdb_enabled; /* Whether is debugging with gdb possible */ int server_port; /* A user specified port number for services */ } debug; struct { /* Verification API, part of Advanced Core Verification */ int enabled; /* Whether is VAPI module enabled */ int server_port; /* A user specified port number for services */ int log_enabled; /* Whether to log the vapi requests */ int log_device_id; /* Whether to log device ID for each request */ char vapi_fn[STR_SIZE]; /* vapi log filename */ } vapi; }; struct runtime { struct { FILE *fprof; /* Profiler file */ FILE *fexe_log; /* RTL state comparison file */ int init; /* Whether we are still initilizing sim */ int script_file_specified;/* Whether script file was already loaded */ char *filename; /* Original Command Simulator file (CZ) */ } sim; struct { /* Verification API, part of Advanced Core Verification */ FILE *vapi_file; /* vapi file */ } vapi; }; #ifdef DEBUGMOD_OFF #define DEBUG_ENABLED 0 #define GDB_ENABLED 0 #else #define DEBUG_ENABLED config.debug.enabled #define GDB_ENABLED config.debug.gdb_enabled #endif extern struct config config; extern struct runtime runtime; /* Read environment from a script file. Does not fail - assumes defaukt configuration instead. */ void read_script_file (char *filename); /* Executes set sim command. Returns nonzero if error. */ void set_config_command (char *s);
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