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[/] [or1k/] [tags/] [nog_patch_73/] [or1ksim/] [mmu/] [immu.c] - Rev 1432
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/* immu.c -- Instruction MMU simulation Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* IMMU model (not functional yet, currently just copy of data cache). */ #include "config.h" #ifdef HAVE_INTTYPES_H #include <inttypes.h> #endif #include "port.h" #include "arch.h" #include "immu.h" #include "abstract.h" #include "opcode/or32.h" #include "spr_defs.h" #include "execute.h" #include "stats.h" #include "sprs.h" #include "except.h" #include "sim-config.h" #include "debug.h" DEFAULT_DEBUG_CHANNEL(immu); extern int cont_run; /* Insn MMU */ static inline oraddr_t immu_simulate_tlb(oraddr_t virtaddr) { int set, way = -1; int i; oraddr_t tagaddr; oraddr_t vpn, ppn; if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) { insn_ci = (virtaddr >= 0x80000000); return virtaddr; } TRACE("IMMU enabled, checking mmu ways\n"); /* Which set to check out? */ set = (virtaddr / config.immu.pagesize) % config.immu.nsets; tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets; vpn = virtaddr / (config.immu.pagesize * config.immu.nsets); /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.immu.nways; i++) if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) && testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V)) way = i; /* Did we find our tlb entry? */ if (way >= 0) { /* Yes, we did. */ immu_stats.fetch_tlbhit++; TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr); /* Set LRUs */ for (i = 0; i < config.immu.nways; i++) if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU)) setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1); setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1); /* Check if page is cache inhibited */ insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI; runtime.sim.mem_cycles += config.immu.hitdelay; /* Test for page fault */ if (mfspr (SPR_SR) & SPR_SR_SM) { if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) except_handle(EXCEPT_IPF, virtaddr); } else { if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) except_handle(EXCEPT_IPF, virtaddr); } ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize; return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize); } else { /* No, we didn't. */ immu_stats.fetch_tlbmiss++; #if 0 for (i = 0; i < config.immu.nways; i++) if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru) minway = i; setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn); for (i = 0; i < config.immu.nways; i++) if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU)) setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1); setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1); setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */ setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1); #endif /* if tlb refill implemented in HW */ /* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */ runtime.sim.mem_cycles += config.immu.missdelay; except_handle(EXCEPT_ITLBMISS, virtaddr); return 0; } } /* DESC: try to find EA -> PA transaltion without changing * any of precessor states. if this is not passible gives up * (without triggering exceptions) * * PRMS: virtaddr - EA for which to find translation * * RTRN: 0 - no IMMU, IMMU disabled or ITLB miss * else - appropriate PA (note it IMMU is not present * PA === EA) */ oraddr_t peek_into_itlb(oraddr_t virtaddr) { int set, way = -1; int i; oraddr_t tagaddr; oraddr_t vpn, ppn; if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) { return(virtaddr); } /* Which set to check out? */ set = (virtaddr / config.immu.pagesize) % config.immu.nsets; tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets; vpn = virtaddr / (config.immu.pagesize * config.immu.nsets); /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.immu.nways; i++) if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) && testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V)) way = i; /* Did we find our tlb entry? */ if (way >= 0) { /* Yes, we did. */ /* Test for page fault */ if (mfspr (SPR_SR) & SPR_SR_SM) { if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) { /* no luck, giving up */ return(0); } } else { if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) { /* no luck, giving up */ return(0); } } ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize; return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize); } else { return(0); } ERR("should never have happened\n"); return(0); } oraddr_t immu_translate(oraddr_t virtaddr) { oraddr_t phyaddr = immu_simulate_tlb(virtaddr); /* PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/ return phyaddr; } void itlb_info() { if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) { PRINTF("IMMU not implemented. Set UPR[IMP].\n"); return; } PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024); PRINTF("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize); } /* First check if virtual address is covered by ITLB and if it is: - increment ITLB read hit stats, - set 'lru' at this way to config.immu.ustates - 1 and decrement 'lru' of other ways unless they have reached 0, - check page access attributes and invoke IMMU page fault exception handler if necessary and if not: - increment ITLB read miss stats - find lru way and entry and invoke ITLB miss exception handler - set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other ways unless they have reached 0 */ void itlb_status(int start_set) { int set; int way; int end_set = config.immu.nsets; if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) { PRINTF("IMMU not implemented. Set UPR[IMP].\n"); return; } if ((start_set >= 0) && (start_set < end_set)) end_set = start_set + 1; else start_set = 0; if (start_set < end_set) PRINTF("\nIMMU: "); /* Scan set(s) and way(s). */ for (set = start_set; set < end_set; set++) { PRINTF("\nSet %x: ", set); for (way = 0; way < config.immu.nways; way++) { PRINTF(" way %d: ", way); PRINTF("vpn=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_VPN)); PRINTF("lru=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU)); PRINTF("pl1=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_PL1)); PRINTF("v=%lx ", getsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_V)); PRINTF("a=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_A)); PRINTF("d=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_D)); PRINTF("uxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_UXE)); PRINTF("sxe=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_SXE)); PRINTF("ppn=%lx ", getsprbits(SPR_ITLBTR_BASE(way) + set, SPR_ITLBTR_PPN)); } } if (start_set < end_set) PRINTF("\n"); } /*---------------------------------------------------[ IMMU configuration ]---*/ void immu_enabled(union param_val val, void *dat) { setsprbits (SPR_UPR, SPR_UPR_IMP, val.int_val ? 1 : 0); config.immu.enabled = val.int_val; } void immu_nsets(union param_val val, void *dat) { if (is_power2(val.int_val) && val.int_val <= 256) { config.immu.nsets = val.int_val; setsprbits (SPR_IMMUCFGR, SPR_IMMUCFGR_NTS, log2(val.int_val)); } else CONFIG_ERROR("value of power of two and lower or equal than 256 expected."); } void immu_nways(union param_val val, void *dat) { if (val.int_val >= 1 && val.int_val <= 4) { config.immu.nways = val.int_val; setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1); } else CONFIG_ERROR("value 1, 2, 3 or 4 expected."); } void immu_pagesize(union param_val val, void *dat) { if (is_power2(val.int_val)) config.immu.pagesize = val.int_val; else CONFIG_ERROR("value of power of two expected."); } void immu_entrysize(union param_val val, void *dat) { if (is_power2(val.int_val)) config.immu.entrysize = val.int_val; else CONFIG_ERROR("value of power of two expected."); } void immu_ustates(union param_val val, void *dat) { if (val.int_val >= 2 && val.int_val <= 4) config.immu.ustates = val.int_val; else CONFIG_ERROR("invalid USTATE."); } void immu_missdelay(union param_val val, void *dat) { config.immu.missdelay = val.int_val; } void immu_hitdelay(union param_val val, void *dat) { config.immu.hitdelay = val.int_val; } void reg_immu_sec(void) { struct config_section *sec = reg_config_sec("immu", NULL, NULL); reg_config_param(sec, "enabled", paramt_int, immu_enabled); reg_config_param(sec, "nsets", paramt_int, immu_nsets); reg_config_param(sec, "nways", paramt_int, immu_nways); reg_config_param(sec, "pagesize", paramt_int, immu_pagesize); reg_config_param(sec, "entrysize", paramt_int, immu_entrysize); reg_config_param(sec, "ustates", paramt_int, immu_ustates); reg_config_param(sec, "missdelay", paramt_int, immu_missdelay); reg_config_param(sec, "hitdelay", paramt_int, immu_hitdelay); }
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