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[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [testbench/] [acv_uart.cfg] - Rev 344
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/* default.cfg -- Simulator testbench default configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
section memory
memory_table_file = "simmem.cfg"
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
end
section cpu
ver = 0x1200
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 0
history = 0
dependstats = 0
dependency = 0
slp = 0
btic = 0
bpb = 0
end
section sim
debug = 4
profile = 0
prof_fn = "sim.profile"
verbose = 1
/* iprompt = 0 */
exe_log = 0
exe_log_fn = "executed.log"
end
section uart
enabled = 1
nuarts = 1
device 0
baseaddr = 0x9c000000
jitter = -1 /* async behaviour */
16550 = 1
irq = 4
vapi_id = 0x00010000
enddevice
end
section VAPI
enabled = 0
server_port = 9998
end
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