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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Test bench                                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Test bench using on OR1200 and wb_sram.                     ////
////                                                              ////
////  To Do:                                                      ////
////   None.                                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:49:34  lampret
// Benches (under development).
//
//
 
`include "timescale.v"
 
module tb_or1200;
 
//
// System connections
//
reg     clk;
reg	risc_clk;
reg     rst;
 
//
// Interconnect between OR1200 and iwb_ram
//
wire            iwb_ack;
wire            iwb_cyc;
wire    [17:0]  iwb_adr;
wire    [31:0]  iwb_dat_risc;
wire    [31:0]  iwb_dat_mem;
wire            iwb_err;
wire            iwb_rty;
wire    [3:0]   iwb_sel;
wire            iwb_stb;
wire            iwb_we;
 
//
// Interconnect between OR1200 and dwb_ram
//
wire            dwb_ack;
wire            dwb_cyc;
wire    [17:0]  dwb_adr;
wire    [31:0]  dwb_dat_risc;
wire    [31:0]  dwb_dat_mem;
wire            dwb_err;
wire            dwb_rty;
wire    [3:0]   dwb_sel;
wire            dwb_stb;
wire            dwb_we;
 
integer i;
 
//
// Initial state
//
initial
begin
        clk = 1'b0;
        risc_clk = 1'b0;
end
 
//
// Reset interval
//
initial
begin
	for(i = 0; i < 32; i = i + 1) begin
		risc.cpu.rf.rf_a.mem[i] = 0;
		risc.cpu.rf.rf_b.mem[i] = 0;
	end
	for(i = 0; i < 512; i = i + 1) begin
`ifdef ARTISAN_SSP
		risc.ic.ic_tag.ic_tag0.artisan_ssp.mem[i] = 19'h1234;
`else
		risc.ic.ic_tag.ic_tag0.mem[i] = 19'h1234;
`endif
	end
	for(i = 0; i < 2048; i = i + 1) begin
`ifdef ARTISAN_SSP
		risc.ic.ic_ram.ic_ram0.artisan_ssp.mem[i] = 32'b0;
`else
		risc.ic.ic_ram.ic_ram0.mem[i] = 32'b0;
`endif
	end
	for(i = 0; i < 512; i = i + 1) begin
`ifdef ARTISAN_SSP
		risc.dc.dc_tag.dc_tag0.artisan_ssp.mem[i] = 19'h1234;
`else
		risc.dc.dc_tag.dc_tag0.mem[i] = 19'h1234;
`endif
	end
	for(i = 0; i < 2048; i = i + 1) begin
`ifdef ARTISAN_SSP
		risc.dc.dc_ram.dc_ram0.artisan_ssp.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram1.artisan_ssp.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram2.artisan_ssp.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram3.artisan_ssp.mem[i] = 8'b0;
`else
		risc.dc.dc_ram.dc_ram0.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram1.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram2.mem[i] = 8'b0;
		risc.dc.dc_ram.dc_ram3.mem[i] = 8'b0;
`endif
	end
`ifdef ARTISAN_SSP
	risc.ic.ic_tag.ic_tag0.artisan_ssp.LAST_qi = 19'h1234;
	risc.dc.dc_tag.dc_tag0.artisan_ssp.LAST_qi = 19'h1234;
`else
	risc.ic.ic_tag.ic_tag0.do_reg = 19'h1234;
	risc.dc.dc_tag.dc_tag0.do_reg = 19'h1234;
`endif
//	risc.ic.ic_tag.ic_tag0.d_reg = 19'h1234;
//	risc.dc.dc_tag.dc_tag0.d_reg = 19'h1234;
//	risc.ic.ic_tag.ic_tag0.do_reg = 19'h1234;
//	risc.dc.dc_tag.dc_tag0.do_reg = 19'h1234;
`ifdef ARTISAN_SSP
        risc.ic.ic_tag.ic_tag0.artisan_ssp.di = 19'h1234;
        risc.dc.dc_tag.dc_tag0.artisan_ssp.di = 19'h1234;
	risc.ic.ic_tag.ic_tag0.artisan_ssp.qi = 19'h1234;
	risc.dc.dc_tag.dc_tag0.artisan_ssp.qi = 19'h1234;
`endif
`ifdef VCD_DUMP
	$dumpfile("dump.vcd");
	$dumpvars(20,tb_or1200);
`endif
        rst = 1'b0;
        #1 rst = 1'b1;
        #25 rst = 1'b0;
	#5765 for(i = 0; i < 32; i = i + 1) begin
//		$display("%d %h", i, risc.cpu.rf.rf_b.mem[i]);
	end
//        #1000 $finish;
end
 
//
// Clock generation
//
always
        #10 risc_clk = ~risc_clk;
 
//
// WB Clock generation
//
always
        #20 clk = ~clk;
 
 
or1200 risc(
        .clk(risc_clk),
        .rst(rst),
        .pic_ints(0),
        .clkdiv_by_2(1'b1),
 
	// Instruction WISHBONE interface
	.iwb_clk_i(clk),
	.iwb_rst_i(rst),
	.iwb_ack_i(iwb_ack),
	.iwb_err_i(iwb_err),
	.iwb_rty_i(iwb_rty),
	.iwb_dat_i(iwb_dat_risc),
	.iwb_cyc_o(iwb_cyc),
	.iwb_adr_o(iwb_adr),
	.iwb_stb_o(iwb_stb),
	.iwb_we_o(iwb_we),
	.iwb_sel_o(iwb_sel),
	.iwb_dat_o(iwb_dat_mem),
 
	// Data WISHBONE interface
	.dwb_clk_i(clk),
	.dwb_rst_i(rst),
	.dwb_ack_i(dwb_ack),
	.dwb_err_i(dwb_err),
	.dwb_rty_i(dwb_rty),
	.dwb_dat_i(dwb_dat_risc),
	.dwb_cyc_o(dwb_cyc),
	.dwb_adr_o(dwb_adr),
	.dwb_stb_o(dwb_stb),
	.dwb_we_o(dwb_we),
	.dwb_sel_o(dwb_sel),
	.dwb_dat_o(dwb_dat_mem),
 
        // These connect RISC's Trace port to external Trace port pads
        .tp_dir_in(1'b0),
        .tp_sel(2'b0),
        .tp_in(32'b0),
        .tp_out(),
 
        // Power management interface
	.pm_cpustall(1'b0),
	.pm_clksd(),
	.pm_dc_gate(),
	.pm_ic_gate(),
	.pm_dmmu_gate(),
	.pm_immu_gate(),
	.pm_tt_gate(),
	.pm_cpu_gate(),
	.pm_wakeup(),
	.pm_lvolt()
);
 
//
// Instatiation of Slave WISHBONE Dual-port Synchronous SRAM
//
wb_sram wb_sram(
	// WISHBONE interface 1
	.wb1_clk_i(clk),
	.wb1_rst_i(rst),
 
	.wb1_cyc_i(iwb_cyc),
	.wb1_adr_i(iwb_adr),
	.wb1_dat_i(iwb_dat_mem),
	.wb1_stb_i(iwb_stb),
	.wb1_we_i(iwb_we),
	.wb1_sel_i(iwb_sel),
 
	.wb1_ack_o(iwb_ack),
	.wb1_err_o(iwb_err),
	.wb1_rty_o(iwb_rty),
	.wb1_dat_o(iwb_dat_risc),
 
	// WISHBONE interface 2
	.wb2_clk_i(clk),
	.wb2_rst_i(rst),
 
	.wb2_cyc_i(dwb_cyc),
	.wb2_adr_i(dwb_adr),
	.wb2_dat_i(dwb_dat_mem),
	.wb2_stb_i(dwb_stb),
	.wb2_we_i(dwb_we),
	.wb2_sel_i(dwb_sel),
 
	.wb2_ack_o(dwb_ack),
	.wb2_err_o(dwb_err),
	.wb2_rty_o(dwb_rty),
	.wb2_dat_o(dwb_dat_risc)
);
 
endmodule