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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Rev 562
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's Data MMU top level //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instantiation of all DMMU blocks. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1 2002/01/03 08:16:15 lampret // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. // // Revision 1.6 2001/10/21 17:57:16 lampret // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. // // Revision 1.5 2001/10/14 13:12:09 lampret // MP3 version. // // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.1 2001/08/17 08:03:35 lampret // *** empty log message *** // // Revision 1.2 2001/07/22 03:31:53 lampret // Fixed RAM's oen bug. Cache bypass under development. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" // // Data MMU // module or1200_dmmu_top( // Rst and clk clk, rst, // CPU i/f dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cyc_i, dcpu_stb_i, dcpu_we_i, dcpu_tag_o, dcpu_err_o, // SPR access spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, // DC i/f dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cyc_o, dcdmmu_stb_o, dcdmmu_ci_o ); parameter dw = `OR1200_OPERAND_WIDTH; parameter aw = `OR1200_OPERAND_WIDTH; // // I/O // // // Clock and reset // input clk; input rst; // // CPU I/F // input dc_en; input dmmu_en; input supv; input [aw-1:0] dcpu_adr_i; input dcpu_cyc_i; input dcpu_stb_i; input dcpu_we_i; output [3:0] dcpu_tag_o; output dcpu_err_o; // // SPR access // input spr_cs; input spr_write; input [aw-1:0] spr_addr; input [31:0] spr_dat_i; output [31:0] spr_dat_o; // // DC I/F // input dcdmmu_err_i; input [3:0] dcdmmu_tag_i; output [aw-1:0] dcdmmu_adr_o; output dcdmmu_cyc_o; output dcdmmu_stb_o; output dcdmmu_ci_o; // // Internal wires and regs // wire dtlb_spr_access; wire [31:`OR1200_DMMU_PS] dtlb_ppn; wire dtlb_hit; wire dtlb_uwe; wire dtlb_ure; wire dtlb_swe; wire dtlb_sre; wire [31:0] dtlb_dat_o; wire dtlb_en; wire dtlb_ci; wire dtlb_done; wire fault; wire miss; reg dcpu_cyc_dlyd; reg dcpu_stb_dlyd; // // Implemented bits inside match and translate registers // // dtlbwYmrX: vpn 31-10 v 0 // dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6 // // dtlb memory width: // 19 bits for ppn // 13 bits for vpn // 1 bit for valid // 4 bits for protection // 1 bit for cache inhibit `ifdef OR1200_NO_DMMU // // Put all outputs in inactive state // assign spr_dat_o = 32'h00000000; assign dcdmmu_adr_o = dcpu_adr_i; assign dcpu_tag_o = dcdmmu_tag_i; assign dcdmmu_cyc_o = dcpu_cyc_i; assign dcdmmu_stb_o = dcpu_stb_i; assign dcpu_err_o = dcdmmu_err_i; assign dcdmmu_ci_o = !dcpu_adr_i[30]; `else // // DTLB SPR access // // 0A00 - 0AFF dtlbmr w0 // 0A00 - 0A3F dtlbmr w0 [63:0] // // 0B00 - 0BFF dtlbtr w0 // 0B00 - 0B3F dtlbtr w0 [63:0] // assign dtlb_spr_access = spr_cs; // // Tags: // // OR1200_DTAG_TE - TLB miss Exception // OR1200_DTAG_PE - Page fault Exception // assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : dcdmmu_tag_i; // // dcpu_err_o // assign dcpu_err_o = miss | fault | dcdmmu_err_i; // // Delay WISHBONE control signals in case DC is disabled and DMMU is // enabled to prevent premature external BIU access. // always @(posedge rst or posedge clk) if (rst) dcpu_cyc_dlyd <= #1 1'b0; else dcpu_cyc_dlyd <= #1 ~(miss | fault) & dcpu_cyc_i; always @(posedge rst or posedge clk) if (rst) dcpu_stb_dlyd <= #1 1'b0; else dcpu_stb_dlyd <= #1 ~(miss | fault) & dcpu_stb_i; // // Cut transfer if something goes wrong with translation. If DC is disabled, // use delayed signals. // assign dcdmmu_cyc_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dcpu_cyc_dlyd : (miss | fault) ? 1'b0 : dcpu_cyc_i; assign dcdmmu_stb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dcpu_stb_dlyd : (miss | fault) ? 1'b0 : dcpu_stb_i; // // Cache Inhibit // assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : 1'b0; // // Physical address is either translated virtual address or // simply equal when DMMU is disabled // assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i; // // Output to SPRS unit // assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000; // // Page fault exception logic // assign fault = dtlb_en & dtlb_done & ( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled || (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled // // TLB Miss exception logic // assign miss = dtlb_en & dtlb_done & !dtlb_hit; // // DTLB Enable // assign dtlb_en = dmmu_en & dcpu_cyc_i & dcpu_stb_i; // // Instantiation of DTLB // or1200_dmmu_tlb or1200_dmmu_tlb( // Rst and clk .clk(clk), .rst(rst), // I/F for translation .tlb_en(dtlb_en), .vaddr(dcpu_adr_i), .hit(dtlb_hit), .ppn(dtlb_ppn), .uwe(dtlb_uwe), .ure(dtlb_ure), .swe(dtlb_swe), .sre(dtlb_sre), .ci(dtlb_ci), .done(dtlb_done), // SPR access .spr_cs(dtlb_spr_access), .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i), .spr_dat_o(dtlb_dat_o) ); `endif endmodule
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