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[/] [or1k/] [tags/] [rel_23/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Rev 504
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's generate PC //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// PC, interface to IC. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.10 2001/11/20 18:46:15 simons // Break point bug fixed // // Revision 1.9 2001/11/18 09:58:28 lampret // Fixed some l.trap typos. // // Revision 1.8 2001/11/18 08:36:28 lampret // For GDB changed single stepping and disabled trap exception. // // Revision 1.7 2001/10/21 17:57:16 lampret // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. // // Revision 1.6 2001/10/14 13:12:09 lampret // MP3 version. // // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.1 2001/08/09 13:39:33 lampret // Major clean-up. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_genpc( // Clock and reset clk, rst, // External i/f to IC icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, // Internal i/f branch_op, except_type, branch_addrofs, lr_restor, flag, taken, except_start, binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch ); // // I/O // // // Clock and reset // input clk; input rst; // // External i/f to IC // output [31:0] icpu_adr_o; output icpu_cyc_o; output icpu_stb_o; output [3:0] icpu_sel_o; output [3:0] icpu_tag_o; input icpu_ack_i; input icpu_rty_i; input icpu_err_i; input [31:0] icpu_adr_i; // // Internal i/f // input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; input [`OR1200_EXCEPT_WIDTH-1:0] except_type; input [31:2] branch_addrofs; input [31:0] lr_restor; input flag; output taken; input except_start; input [31:2] binsn_addr; input [31:0] epcr; input [31:0] spr_dat_i; input spr_pc_we; input genpc_refetch; // // Internal wires and regs // reg [31:2] pcreg; reg [31:0] pc; reg taken; /* Set to in case of jump or taken branch */ reg dslot; /* set when fetching delay slot insn */ reg btarget; /* set when fetching branch target insns */ // // Address of insn to be fecthed // assign icpu_adr_o = icpu_rty_i | genpc_refetch ? icpu_adr_i : pc; // // Control access to IC subsystem // assign icpu_cyc_o = 1'b1; assign icpu_stb_o = 1'b1; assign icpu_sel_o = 4'b1111; assign icpu_tag_o = `OR1200_ITAG_NI; // // Async calculation of new PC value. This value is used for addressing the IC. // always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case {2'b00, `OR1200_BRANCHOP_NOP}: begin pc = {pcreg + 'd1, 2'b0}; taken = 1'b0; end {2'b00, `OR1200_BRANCHOP_J}: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs); // synopsys translate_on `endif pc = {branch_addrofs, 2'b0}; taken = 1'b1; end {2'b00, `OR1200_BRANCHOP_JR}: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor); // synopsys translate_on `endif pc = lr_restor; taken = 1'b1; end {2'b00, `OR1200_BRANCHOP_BAL}: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); // synopsys translate_on `endif pc = {binsn_addr + branch_addrofs, 2'b0}; taken = 1'b1; end {2'b00, `OR1200_BRANCHOP_BF}: if (flag) begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); // synopsys translate_on `endif pc = {binsn_addr + branch_addrofs, 2'b0}; taken = 1'b1; end else begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_BF: not taken", $time); // synopsys translate_on `endif pc = {pcreg + 'd1, 2'b0}; taken = 1'b0; end {2'b00, `OR1200_BRANCHOP_BNF}: if (flag) begin pc = {pcreg + 'd1, 2'b0}; `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_BNF: not taken", $time); // synopsys translate_on `endif taken = 1'b0; end else begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs); // synopsys translate_on `endif pc = {binsn_addr + branch_addrofs, 2'b0}; taken = 1'b1; end {2'b00, `OR1200_BRANCHOP_RFE}: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr); // synopsys translate_on `endif pc = epcr; taken = 1'b1; end {2'b01, 3'bxxx}: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("Starting exception: %h.", except_type); // synopsys translate_on `endif pc = { 20'h0_0000, except_type, 8'h00}; taken = 1'b1; end default: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("l.mtspr writing into PC: %h.", spr_dat_i); // synopsys translate_on `endif pc = spr_dat_i; taken = 1'b0; end endcase end // // PC register // always @(posedge clk or posedge rst) if (rst) pcreg <= #1 30'd63; else if (spr_pc_we) pcreg <= #1 spr_dat_i[31:2]; else if (!icpu_rty_i & !genpc_refetch) pcreg <= #1 pc[31:2]; // // dslot // always @(posedge clk or posedge rst) if (rst) dslot <= #1 1'b0; else if (spr_pc_we) dslot <= #1 1'b0; else if (!icpu_rty_i) dslot <= #1 |branch_op; // // btarget // always @(posedge clk or posedge rst) if (rst) btarget <= #1 1'b0; else if (spr_pc_we) btarget <= #1 1'b0; else if (!icpu_rty_i) btarget <= #1 dslot; endmodule
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