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https://opencores.org/ocsvn/or1k/or1k/trunk
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[/] [or1k/] [tags/] [rel_4/] [or1200/] [syn/] [scr/] [read_design.inc] - Rev 1765
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/* Set search path for verilog include files */
search_path = search_path + { RTL_PATH } + { GATE_PATH }
/* Read verilog files of the Data cache / DMMU */
if (TOPLEVEL == "dc") {
read -f verilog dc_fsm.v
read -f verilog reg2mem.v
read -f verilog mem2reg.v
read -f verilog dc_ram.v
read -f verilog dc_tag.v
read -f verilog dtlb.v
read -f verilog dc.v
}
/* Read verilog files for the multiplier */
if (TOPLEVEL == "multp2_32x32") {
read -f verilog multp2_32x32.v
}
/* Read verilog files of the CPU */
if (TOPLEVEL == "cpu") {
read -f verilog alu.v
read -f verilog except.v
read -f verilog frz_logic.v
read -f verilog id.v
read -f verilog ifetch.v
read -f verilog lsu.v
read -f db incremental_multp2_32x32.db
read -f verilog operandmuxes.v
read -f verilog rf.v
read -f verilog sprs.v
read -f verilog traceport.v
read -f verilog wbmux.v
read -f verilog cpu.v
}
/* Read verilog files of the Instructino cache / IMMU */
if (TOPLEVEL == "ic") {
read -f verilog ic_fsm.v
read -f verilog ic_ram.v
read -f verilog ic_tag.v
read -f verilog itlb.v
read -f verilog ic.v
}
/* Top level OR1200 + various smaller OR1200 units */
if (TOPLEVEL == "or1200") {
read -f verilog pic.v
read -f verilog pm.v
read -f verilog tt.v
read -f verilog wb_biu.v
read -f db incremental_dc.db
read -f db incremental_cpu.db
read -f db incremental_ic.db
read -f verilog or1200.v
}