Subversion Repositories or1k

/*
 * User defines
 *
 */
TOPLEVEL = or1200
include select_tech.inc
CLK = clk
RST = rst
CLK_PERIOD = 2.5	/* 400 MHz */
MAX_AREA = 0		/* Push it */
DO_UNGROUP = yes	/* yes, no */
DO_VERIFY = no		/* yes, no */
RAMS = art_rams18	/* fake, art_rams18 */
 
/* Starting timestamp */
sh date
 
/* Set some basic variables related to environment */
include set_env.inc
STAGE = initial
 
/* Load libraries */
include tech_ + TECH + .inc
 
/* Load RAMs */
if (RAMS == "art_rams18") {
	include tech_art_rams18.inc
} else if (RAMS == "fake") {
	include read_fake_rams.inc
} else {	
	echo "Unsupported RAMs"
	exit
}
 
/* Load HDL source files */
include read_design.inc		> LOG_PATH + read_design_ + TOPLEVEL + .log
 
/* Set design top */
current_design TOPLEVEL
 
/* Link all blocks and uniquify them */
link
/*
include tech_art_rams18.inc
list -libraries > ../logs/libs
link
list -libraries > ../logs/libs
*/
uniquify
check_design			> LOG_PATH + check_design_ + TOPLEVEL + .log
 
/* Apply constraints */
if (TECH == "vs_umc18") {
	include cons_vs_umc18.inc
} else if (TECH == "art_umc18") {
	include cons_art_umc18.inc
} else {
	echo "Error: Unsupported technology"
	exit
}
 
/* Transform arithmetics */
transform_csa -group
 
/* Lets do initial synthesis */
if (DO_UNGROUP == "yes") {
        ungroup -all
}
compile -incremental -boundary_optimization -map_effort medium
 
/* Generate reports for basic synthesis */
include reports.inc
 
/* Dump gate-level from basic synthesis */
include save_design.inc
 
/* Advance to incremental synthesis, push hard */
if (DO_UNGROUP == "yes") {
        ungroup -all
}
STAGE = incremental
compile -incremental -boundary_optimization -ungroup_all -map_effort high
 
/* Optimize registers */
optimize_registers
 
/* Dump gate-level from incremental synthesis */
include save_design.inc
 
/* Generate reports for incremental synthesis */
include reports.inc
 
/* Set area constraint */
STAGE = final
set_max_area MAX_AREA
compile -incremental -boundary_optimization -auto_ungroup -map_effort medium
 
/* Dump gate-level from final synthesis */
include save_design.inc
 
/* Generate reports for final synthesis */
include reports.inc
 
/* Verify design */
if (NO_VERIFY == "yes") {
	compile -no_map -verify		> LOG_PATH + verify_ + TOPLEVEL + .log
}
 
/* Finish */
sh date
exit