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[/] [or1k/] [tags/] [stable/] [mp3/] [lib/] [xilinx/] [unisims/] [OFDXI_24.v] - Rev 392
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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/OFDXI_24.v,v 1.1.1.1 2001-11-04 18:59:50 lampret Exp $ /* FUNCTION : Output D-FLIP-FLOP with clock enable */ `timescale 100 ps / 10 ps `celldefine module OFDXI_24 (Q, C, CE, D); parameter cds_action = "ignore"; parameter INIT = 1'b0; output Q; reg q_out; input C, CE, D; tri0 GSR = glbl.GSR; tri0 GTS = glbl.GTS; bufif0 B1 (Q, q_out, GTS); always @(GSR) if (GSR) assign q_out = INIT; else deassign q_out; always @(posedge C) if (CE) q_out <= D; specify (posedge C => (Q +: D)) = (1, 1); endspecify endmodule `endcelldefine
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